Formal verification: an essential toolkit for modern VLSI design
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents th...
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Amsterdam
Elsevier Science
2015
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| Subjects: | |
| Online Access: | FLA01 Volltext |
| Summary: | Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity |
| Item Description: | Includes index. - How Do We Reach Targeted Behaviors? |
| Physical Description: | 1 online resource (372 pages) illustrations |
| ISBN: | 9780128008157 0128008156 |
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| id | DE-604.BV046126895 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:35:54Z |
| institution | BVB |
| isbn | 9780128008157 0128008156 |
| language | English |
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| physical | 1 online resource (372 pages) illustrations |
| psigel | ZDB-33-ESD ZDB-33-ESD FLA_PDA_ESD |
| publishDate | 2015 |
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| publisher | Elsevier Science |
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| spelling | Seligman, Erik Verfasser aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar Amsterdam Elsevier Science 2015 1 online resource (372 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Includes index. - How Do We Reach Targeted Behaviors? Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity TECHNOLOGY & ENGINEERING / Mechanical bisacsh Electronic circuits / Testing fast Integrated circuits / Very large scale integration / Design and construction fast Verilog (Computer hardware description language) fast Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Schubert, Tom Sonstige oth Kumar, M. V. Achutha Kiran Sonstige oth Erscheint auch als Druck-Ausgabe 9780128007273 http://www.sciencedirect.com/science/book/9780128007273 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Seligman, Erik Formal verification an essential toolkit for modern VLSI design TECHNOLOGY & ENGINEERING / Mechanical bisacsh Electronic circuits / Testing fast Integrated circuits / Very large scale integration / Design and construction fast Verilog (Computer hardware description language) fast Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | TECHNOLOGY & ENGINEERING / Mechanical bisacsh Electronic circuits / Testing fast Integrated circuits / Very large scale integration / Design and construction fast Verilog (Computer hardware description language) fast Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| topic_facet | TECHNOLOGY & ENGINEERING / Mechanical Electronic circuits / Testing Integrated circuits / Very large scale integration / Design and construction Verilog (Computer hardware description language) Electronic circuits Testing Integrated circuits Very large scale integration Design and construction |
| url | http://www.sciencedirect.com/science/book/9780128007273 |
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