APA (7th ed.) Citation

Seligman, E. (2015). Formal verification: An essential toolkit for modern VLSI design. Elsevier Science.

Chicago Style (17th ed.) Citation

Seligman, Erik. Formal Verification: An Essential Toolkit for Modern VLSI Design. Amsterdam: Elsevier Science, 2015.

MLA (9th ed.) Citation

Seligman, Erik. Formal Verification: An Essential Toolkit for Modern VLSI Design. Elsevier Science, 2015.

Warning: These citations may not always be 100% accurate.