As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...

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Bibliographische Detailangaben

1. Verfasser:	Harris, David Money 19XX- (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	San Francisco Morgan Kaufmann Publishers © 2001
Schriftenreihe:	Morgan Kaufmann series in computer architecture and design
Schlagworte:	TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated TECHNOLOGY & ENGINEERING / Electronics / Circuits / General Integrated circuits / Very large scale integration / Design and construction Synchronization Timing circuits / Design and construction Timing circuits > Design and construction Integrated circuits > Very large scale integration > Design and construction Integrierte Schaltung
Online-Zugang:	FLA01 Volltext
Zusammenfassung:	As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises
Beschreibung:	Includes bibliographical references and index
Beschreibung:	1 online resource (xiv, 223 pages) illustrations
ISBN:	9780080541266 0080541267 9781558606364 155860636X 1281078042 9781281078049