VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...
Gespeichert in:
| Weitere Verfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam Boston
Elsevier Morgan Kaufmann Publishers
© 2006
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | FLA01 Volltext |
| Zusammenfassung: | This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | 1 online resource (xxx, 777 pages) illustrations |
| ISBN: | 9780080474793 0080474799 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV046123895 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 190827s2006 |||| o||u| ||||||eng d | ||
| 020 | |a 9780080474793 |9 978-0-08-047479-3 | ||
| 020 | |a 0080474799 |9 0-08-047479-9 | ||
| 035 | |a (ZDB-33-ESD)ocn162573568 | ||
| 035 | |a (OCoLC)162573568 | ||
| 035 | |a (DE-599)BVBBV046123895 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.39/5 |2 22 | |
| 084 | |a ZN 4030 |0 (DE-625)157339: |2 rvk | ||
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 245 | 1 | 0 | |a VLSI test principles and architectures |b design for testability |c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| 264 | 1 | |a Amsterdam |a Boston |b Elsevier Morgan Kaufmann Publishers |c © 2006 | |
| 300 | |a 1 online resource (xxx, 777 pages) |b illustrations | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Morgan Kaufmann series in systems on silicon | |
| 500 | |a Includes bibliographical references and index | ||
| 520 | |a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website | ||
| 650 | 4 | |a Circuits intégrés à très grande échelle / Essais | |
| 650 | 4 | |a Circuits intégrés à très grande échelle / Conception et construction | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic |2 bisacsh | |
| 650 | 7 | |a COMPUTERS / Logic Design |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Testing |2 blmlsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design |2 blmlsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design |2 fast | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Testing |2 fast | |
| 650 | 7 | |a Testen |2 gnd | |
| 650 | 7 | |a VLSI |2 gnd | |
| 650 | 7 | |a Circuitos integrados vlsi |2 larpcal | |
| 650 | 4 | |a Integrated circuits / Very large scale integration / Testing | |
| 650 | 4 | |a Integrated circuits / Very large scale integration / Design | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Testing | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design | |
| 650 | 0 | 7 | |a Testen |0 (DE-588)4367264-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Testen |0 (DE-588)4367264-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Wang, Laung-Terng |4 edt | |
| 700 | 1 | |a Wu, Cheng-Wen |4 edt | |
| 700 | 1 | |a Wen, Xiaoqing |4 edt | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 0123705975 |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9780123705976 |
| 856 | 4 | 0 | |u http://www.sciencedirect.com/science/book/9780123705976 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-33-ESD | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-031504348 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u http://www.sciencedirect.com/science/book/9780123705976 |l FLA01 |p ZDB-33-ESD |q FLA_PDA_ESD |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804180441342672896 |
|---|---|
| any_adam_object | |
| author2 | Wang, Laung-Terng Wu, Cheng-Wen Wen, Xiaoqing |
| author2_role | edt edt edt |
| author2_variant | l t w ltw c w w cww x w xw |
| author_facet | Wang, Laung-Terng Wu, Cheng-Wen Wen, Xiaoqing |
| building | Verbundindex |
| bvnumber | BV046123895 |
| classification_rvk | ZN 4030 ZN 4950 ZN 4952 |
| collection | ZDB-33-ESD |
| ctrlnum | (ZDB-33-ESD)ocn162573568 (OCoLC)162573568 (DE-599)BVBBV046123895 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03793nmm a2200697zc 4500</leader><controlfield tag="001">BV046123895</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">190827s2006 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080474793</subfield><subfield code="9">978-0-08-047479-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080474799</subfield><subfield code="9">0-08-047479-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-33-ESD)ocn162573568</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)162573568</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV046123895</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4030</subfield><subfield code="0">(DE-625)157339:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">VLSI test principles and architectures</subfield><subfield code="b">design for testability</subfield><subfield code="c">edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam</subfield><subfield code="a">Boston</subfield><subfield code="b">Elsevier Morgan Kaufmann Publishers</subfield><subfield code="c">© 2006</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xxx, 777 pages)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Morgan Kaufmann series in systems on silicon</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits intégrés à très grande échelle / Essais</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits intégrés à très grande échelle / Conception et construction</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Logic Design</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Testing</subfield><subfield code="2">blmlsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Design</subfield><subfield code="2">blmlsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Design</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Testing</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Testen</subfield><subfield code="2">gnd</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">VLSI</subfield><subfield code="2">gnd</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuitos integrados vlsi</subfield><subfield code="2">larpcal</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Very large scale integration / Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Very large scale integration / Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Testen</subfield><subfield code="0">(DE-588)4367264-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Testen</subfield><subfield code="0">(DE-588)4367264-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wang, Laung-Terng</subfield><subfield code="4">edt</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wu, Cheng-Wen</subfield><subfield code="4">edt</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wen, Xiaoqing</subfield><subfield code="4">edt</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">0123705975</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9780123705976</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.sciencedirect.com/science/book/9780123705976</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-33-ESD</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-031504348</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9780123705976</subfield><subfield code="l">FLA01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FLA_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV046123895 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:35:49Z |
| institution | BVB |
| isbn | 9780080474793 0080474799 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-031504348 |
| oclc_num | 162573568 |
| open_access_boolean | |
| physical | 1 online resource (xxx, 777 pages) illustrations |
| psigel | ZDB-33-ESD ZDB-33-ESD FLA_PDA_ESD |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Elsevier Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen Amsterdam Boston Elsevier Morgan Kaufmann Publishers © 2006 1 online resource (xxx, 777 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Testen (DE-588)4367264-4 s 1\p DE-604 Wang, Laung-Terng edt Wu, Cheng-Wen edt Wen, Xiaoqing edt Erscheint auch als Druck-Ausgabe 0123705975 Erscheint auch als Druck-Ausgabe 9780123705976 http://www.sciencedirect.com/science/book/9780123705976 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | VLSI test principles and architectures design for testability Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4367264-4 (DE-588)4117388-0 |
| title | VLSI test principles and architectures design for testability |
| title_auth | VLSI test principles and architectures design for testability |
| title_exact_search | VLSI test principles and architectures design for testability |
| title_full | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_fullStr | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_full_unstemmed | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_short | VLSI test principles and architectures |
| title_sort | vlsi test principles and architectures design for testability |
| title_sub | design for testability |
| topic | Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Testen VLSI Circuitos integrados vlsi Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design |
| url | http://www.sciencedirect.com/science/book/9780123705976 |
| work_keys_str_mv | AT wanglaungterng vlsitestprinciplesandarchitecturesdesignfortestability AT wuchengwen vlsitestprinciplesandarchitecturesdesignfortestability AT wenxiaoqing vlsitestprinciplesandarchitecturesdesignfortestability |