Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Singapore
Springer Singapore
2019
Singapore Springer |
| Schlagworte: | |
| Online-Zugang: | BTU01 FAW01 FHA01 FHI01 FHM01 FHN01 FHR01 FKE01 FLA01 FRO01 FWS01 FWS02 HTW01 TUM01 UBA01 UBY01 Volltext |
| Beschreibung: | 1 Online-Ressource (XXI, 307 p. 263 illus., 196 illus. in color) |
| ISBN: | 9789811087769 |
| DOI: | 10.1007/978-981-10-8776-9 |
Internformat
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Datensatz im Suchindex
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| author | Taraate, Vaibbhav |
| author_facet | Taraate, Vaibbhav |
| author_role | aut |
| author_sort | Taraate, Vaibbhav |
| author_variant | v t vt |
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| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik Maschinenbau |
| doi_str_mv | 10.1007/978-981-10-8776-9 |
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| id | DE-604.BV045389038 |
| illustrated | Not Illustrated |
| indexdate | 2024-08-01T14:05:33Z |
| institution | BVB |
| isbn | 9789811087769 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030775346 |
| oclc_num | 1081350795 |
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| physical | 1 Online-Ressource (XXI, 307 p. 263 illus., 196 illus. in color) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2019_Fremddaten |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
| publisher | Springer Singapore Springer |
| record_format | marc |
| spellingShingle | Taraate, Vaibbhav Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog Circuits and Systems Control Structures and Microprogramming Logic Design Systems engineering Microprogramming Logic design |
| title | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog |
| title_auth | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog |
| title_exact_search | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog |
| title_full | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog by Vaibbhav Taraate |
| title_fullStr | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog by Vaibbhav Taraate |
| title_full_unstemmed | Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog by Vaibbhav Taraate |
| title_short | Advanced HDL Synthesis and SOC Prototyping |
| title_sort | advanced hdl synthesis and soc prototyping rtl design using verilog |
| title_sub | RTL Design Using Verilog |
| topic | Circuits and Systems Control Structures and Microprogramming Logic Design Systems engineering Microprogramming Logic design |
| topic_facet | Circuits and Systems Control Structures and Microprogramming Logic Design Systems engineering Microprogramming Logic design |
| url | https://doi.org/10.1007/978-981-10-8776-9 |
| work_keys_str_mv | AT taraatevaibbhav advancedhdlsynthesisandsocprototypingrtldesignusingverilog |