Wafer-level testing and test during burn-in for integrated circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Artech House
2010
|
| Schriftenreihe: | Artech House integrated microsystems series
|
| Schlagworte: | |
| Beschreibung: | Print version record |
| Beschreibung: | 1 online resource (xv, 198 pages) illustrations |
| ISBN: | 9781596939905 1596939907 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045344103 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 181206s2010 |||| o||u| ||||||eng d | ||
| 020 | |a 9781596939905 |9 978-1-59693-990-5 | ||
| 020 | |a 1596939907 |9 1-59693-990-7 | ||
| 035 | |a (ZDB-4-ENC)ocn672293639 | ||
| 035 | |a (OCoLC)672293639 | ||
| 035 | |a (DE-599)BVBBV045344103 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.381 |2 22 | |
| 084 | |a ZN 4900 |0 (DE-625)157417: |2 rvk | ||
| 100 | 1 | |a Bahukudumbi, Sudarshan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Wafer-level testing and test during burn-in for integrated circuits |c Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| 264 | 1 | |a Boston |b Artech House |c 2010 | |
| 300 | |a 1 online resource (xv, 198 pages) |b illustrations | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Artech House integrated microsystems series | |
| 500 | |a Print version record | ||
| 505 | 8 | |a Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Microelectronics |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Digital |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Testing |2 fast | |
| 650 | 7 | |a Integrated circuits / Wafer-scale integration |2 fast | |
| 650 | 7 | |a Semiconductors / Testing |2 fast | |
| 650 | 4 | |a Integrated circuits |x Testing |a Integrated circuits |x Wafer-scale integration |a Semiconductors |x Testing | |
| 700 | 1 | |a Chakrabarty, Krishnendu |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Bahukudumbi, Sudarshan |t Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty |d Boston : Artech House, 2010 |z 1596939893 |
| 912 | |a ZDB-4-ENC | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030730807 | ||
Datensatz im Suchindex
| _version_ | 1804179163508113408 |
|---|---|
| any_adam_object | |
| author | Bahukudumbi, Sudarshan |
| author_facet | Bahukudumbi, Sudarshan |
| author_role | aut |
| author_sort | Bahukudumbi, Sudarshan |
| author_variant | s b sb |
| building | Verbundindex |
| bvnumber | BV045344103 |
| classification_rvk | ZN 4900 |
| collection | ZDB-4-ENC |
| contents | Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions |
| ctrlnum | (ZDB-4-ENC)ocn672293639 (OCoLC)672293639 (DE-599)BVBBV045344103 |
| dewey-full | 621.381 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381 |
| dewey-search | 621.381 |
| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02637nmm a2200433zc 4500</leader><controlfield tag="001">BV045344103</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">181206s2010 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781596939905</subfield><subfield code="9">978-1-59693-990-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1596939907</subfield><subfield code="9">1-59693-990-7</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-4-ENC)ocn672293639</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)672293639</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045344103</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.381</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4900</subfield><subfield code="0">(DE-625)157417:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bahukudumbi, Sudarshan</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Wafer-level testing and test during burn-in for integrated circuits</subfield><subfield code="c">Sudarshan Bahukudumbi, Krishnendu Chakrabarty</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston</subfield><subfield code="b">Artech House</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xv, 198 pages)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Artech House integrated microsystems series</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Print version record</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Microelectronics</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Digital</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Testing</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Wafer-scale integration</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Semiconductors / Testing</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Testing</subfield><subfield code="a">Integrated circuits</subfield><subfield code="x">Wafer-scale integration</subfield><subfield code="a">Semiconductors</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Chakrabarty, Krishnendu</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Bahukudumbi, Sudarshan</subfield><subfield code="t">Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty</subfield><subfield code="d">Boston : Artech House, 2010</subfield><subfield code="z">1596939893</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-ENC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030730807</subfield></datafield></record></collection> |
| id | DE-604.BV045344103 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:30Z |
| institution | BVB |
| isbn | 9781596939905 1596939907 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030730807 |
| oclc_num | 672293639 |
| open_access_boolean | |
| physical | 1 online resource (xv, 198 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Artech House |
| record_format | marc |
| series2 | Artech House integrated microsystems series |
| spelling | Bahukudumbi, Sudarshan Verfasser aut Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty Boston Artech House 2010 1 online resource (xv, 198 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Artech House integrated microsystems series Print version record Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits / Testing fast Integrated circuits / Wafer-scale integration fast Semiconductors / Testing fast Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing Chakrabarty, Krishnendu Sonstige oth Erscheint auch als Druck-Ausgabe Bahukudumbi, Sudarshan Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty Boston : Artech House, 2010 1596939893 |
| spellingShingle | Bahukudumbi, Sudarshan Wafer-level testing and test during burn-in for integrated circuits Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits / Testing fast Integrated circuits / Wafer-scale integration fast Semiconductors / Testing fast Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| title | Wafer-level testing and test during burn-in for integrated circuits |
| title_auth | Wafer-level testing and test during burn-in for integrated circuits |
| title_exact_search | Wafer-level testing and test during burn-in for integrated circuits |
| title_full | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_fullStr | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_full_unstemmed | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_short | Wafer-level testing and test during burn-in for integrated circuits |
| title_sort | wafer level testing and test during burn in for integrated circuits |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits / Testing fast Integrated circuits / Wafer-scale integration fast Semiconductors / Testing fast Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics TECHNOLOGY & ENGINEERING / Electronics / Digital Integrated circuits / Testing Integrated circuits / Wafer-scale integration Semiconductors / Testing Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| work_keys_str_mv | AT bahukudumbisudarshan waferleveltestingandtestduringburninforintegratedcircuits AT chakrabartykrishnendu waferleveltestingandtestduringburninforintegratedcircuits |