Design methodology for RF CMOS phase locked loops:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Artech House
2009
|
| Schriftenreihe: | Artech House microwave library
|
| Schlagworte: | |
| Beschreibung: | Print version record |
| Beschreibung: | 1 online resource (xii, 226 pages) illustrations |
| ISBN: | 1596933844 9781596933842 1596933836 9781596933835 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045343369 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 181206s2009 |||| o||u| ||||||eng d | ||
| 020 | |a 1596933844 |9 1-59693-384-4 | ||
| 020 | |a 9781596933842 |9 978-1-59693-384-2 | ||
| 020 | |a 1596933836 |9 1-59693-383-6 | ||
| 020 | |a 9781596933835 |9 978-1-59693-383-5 | ||
| 035 | |a (ZDB-4-ENC)ocn503447788 | ||
| 035 | |a (OCoLC)503447788 | ||
| 035 | |a (DE-599)BVBBV045343369 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.381 |2 22 | |
| 100 | 1 | |a Quemada, Carlos |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design methodology for RF CMOS phase locked loops |c Carlos Quemada, Guillermo Bistu, Iigo Adin |
| 264 | 1 | |a Boston |b Artech House |c 2009 | |
| 300 | |a 1 online resource (xii, 226 pages) |b illustrations | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Artech House microwave library | |
| 500 | |a Print version record | ||
| 505 | 8 | |a Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Microelectronics |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Digital |2 bisacsh | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary / Design and construction |2 fast | |
| 650 | 7 | |a Phase-locked loops / Design and construction |2 fast | |
| 650 | 4 | |a Phase-locked loops |x Design and construction |a Metal oxide semiconductors, Complementary |x Design and construction | |
| 700 | 1 | |a Bistue, Guillermo |e Sonstige |4 oth | |
| 700 | 1 | |a Adin, Inigo |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Quemada, Carlos |t Design methodology for RF CMOS phase locked loops |d Boston : Artech House, 2009 |z 9781596933835 |z 1596933836 |
| 912 | |a ZDB-4-ENC | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030730072 | ||
Datensatz im Suchindex
| _version_ | 1804179162064224256 |
|---|---|
| any_adam_object | |
| author | Quemada, Carlos |
| author_facet | Quemada, Carlos |
| author_role | aut |
| author_sort | Quemada, Carlos |
| author_variant | c q cq |
| building | Verbundindex |
| bvnumber | BV045343369 |
| collection | ZDB-4-ENC |
| contents | Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications |
| ctrlnum | (ZDB-4-ENC)ocn503447788 (OCoLC)503447788 (DE-599)BVBBV045343369 |
| dewey-full | 621.381 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381 |
| dewey-search | 621.381 |
| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03208nmm a2200445zc 4500</leader><controlfield tag="001">BV045343369</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">181206s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1596933844</subfield><subfield code="9">1-59693-384-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781596933842</subfield><subfield code="9">978-1-59693-384-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1596933836</subfield><subfield code="9">1-59693-383-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781596933835</subfield><subfield code="9">978-1-59693-383-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-4-ENC)ocn503447788</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)503447788</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045343369</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.381</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Quemada, Carlos</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design methodology for RF CMOS phase locked loops</subfield><subfield code="c">Carlos Quemada, Guillermo Bistu, Iigo Adin</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston</subfield><subfield code="b">Artech House</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xii, 226 pages)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Artech House microwave library</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Print version record</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Microelectronics</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Digital</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Metal oxide semiconductors, Complementary / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Phase-locked loops / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase-locked loops</subfield><subfield code="x">Design and construction</subfield><subfield code="a">Metal oxide semiconductors, Complementary</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bistue, Guillermo</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Adin, Inigo</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Quemada, Carlos</subfield><subfield code="t">Design methodology for RF CMOS phase locked loops</subfield><subfield code="d">Boston : Artech House, 2009</subfield><subfield code="z">9781596933835</subfield><subfield code="z">1596933836</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-ENC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030730072</subfield></datafield></record></collection> |
| id | DE-604.BV045343369 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:29Z |
| institution | BVB |
| isbn | 1596933844 9781596933842 1596933836 9781596933835 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030730072 |
| oclc_num | 503447788 |
| open_access_boolean | |
| physical | 1 online resource (xii, 226 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Artech House |
| record_format | marc |
| series2 | Artech House microwave library |
| spelling | Quemada, Carlos Verfasser aut Design methodology for RF CMOS phase locked loops Carlos Quemada, Guillermo Bistu, Iigo Adin Boston Artech House 2009 1 online resource (xii, 226 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Artech House microwave library Print version record Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Metal oxide semiconductors, Complementary / Design and construction fast Phase-locked loops / Design and construction fast Phase-locked loops Design and construction Metal oxide semiconductors, Complementary Design and construction Bistue, Guillermo Sonstige oth Adin, Inigo Sonstige oth Erscheint auch als Druck-Ausgabe Quemada, Carlos Design methodology for RF CMOS phase locked loops Boston : Artech House, 2009 9781596933835 1596933836 |
| spellingShingle | Quemada, Carlos Design methodology for RF CMOS phase locked loops Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Metal oxide semiconductors, Complementary / Design and construction fast Phase-locked loops / Design and construction fast Phase-locked loops Design and construction Metal oxide semiconductors, Complementary Design and construction |
| title | Design methodology for RF CMOS phase locked loops |
| title_auth | Design methodology for RF CMOS phase locked loops |
| title_exact_search | Design methodology for RF CMOS phase locked loops |
| title_full | Design methodology for RF CMOS phase locked loops Carlos Quemada, Guillermo Bistu, Iigo Adin |
| title_fullStr | Design methodology for RF CMOS phase locked loops Carlos Quemada, Guillermo Bistu, Iigo Adin |
| title_full_unstemmed | Design methodology for RF CMOS phase locked loops Carlos Quemada, Guillermo Bistu, Iigo Adin |
| title_short | Design methodology for RF CMOS phase locked loops |
| title_sort | design methodology for rf cmos phase locked loops |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Metal oxide semiconductors, Complementary / Design and construction fast Phase-locked loops / Design and construction fast Phase-locked loops Design and construction Metal oxide semiconductors, Complementary Design and construction |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics TECHNOLOGY & ENGINEERING / Electronics / Digital Metal oxide semiconductors, Complementary / Design and construction Phase-locked loops / Design and construction Phase-locked loops Design and construction Metal oxide semiconductors, Complementary Design and construction |
| work_keys_str_mv | AT quemadacarlos designmethodologyforrfcmosphaselockedloops AT bistueguillermo designmethodologyforrfcmosphaselockedloops AT adininigo designmethodologyforrfcmosphaselockedloops |