Verification techniques for system-level design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston
Morgan Kaufmann Publishers
2008
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Beschreibung: | Print version record |
| Beschreibung: | 1 online resource (viii, 240 pages) illustrations |
| ISBN: | 9780080553139 0080553133 |
Internformat
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| 100 | 1 | |a Fujita, Masahiro |d 1956- |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Verification techniques for system-level design |c Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| 264 | 1 | |a Amsterdam ; Boston |b Morgan Kaufmann Publishers |c 2008 | |
| 300 | |a 1 online resource (viii, 240 pages) |b illustrations | ||
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| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Morgan Kaufmann series in systems on silicon | |
| 500 | |a Print version record | ||
| 505 | 8 | |a This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology | |
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| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / General |2 bisacsh | |
| 650 | 7 | |a Systems on a chip / Testing |2 blmlsh | |
| 650 | 7 | |a Integrated circuits / Verification |2 blmlsh | |
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Datensatz im Suchindex
| _version_ | 1804179160111775744 |
|---|---|
| any_adam_object | |
| author | Fujita, Masahiro 1956- |
| author_facet | Fujita, Masahiro 1956- |
| author_role | aut |
| author_sort | Fujita, Masahiro 1956- |
| author_variant | m f mf |
| building | Verbundindex |
| bvnumber | BV045342403 |
| collection | ZDB-4-ENC |
| contents | This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Printbegrnsninger: Der kan printes kapitelvis |
| ctrlnum | (ZDB-4-ENC)ocn182548558 (OCoLC)182548558 (DE-599)BVBBV045342403 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV045342403 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:27Z |
| institution | BVB |
| isbn | 9780080553139 0080553133 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030729106 |
| oclc_num | 182548558 |
| open_access_boolean | |
| physical | 1 online resource (viii, 240 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Fujita, Masahiro 1956- Verfasser aut Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad Amsterdam ; Boston Morgan Kaufmann Publishers 2008 1 online resource (viii, 240 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Print version record This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Printbegrnsninger: Der kan printes kapitelvis TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits / Verification fast Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd rswk-swf LSI (DE-588)4168200-2 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf System-on-Chip (DE-588)4740357-3 s LSI (DE-588)4168200-2 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 Ghosh, Indradeep 1970- Sonstige oth Prasad, Mukul Sonstige oth Erscheint auch als Druck-Ausgabe Fujita, Masahiro, 1956- Verification techniques for system-level design Amsterdam ; Boston : Morgan Kaufmann Publishers, 2008 9780123706164 0123706165 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Fujita, Masahiro 1956- Verification techniques for system-level design This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Printbegrnsninger: Der kan printes kapitelvis TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits / Verification fast Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| subject_GND | (DE-588)4740357-3 (DE-588)4168200-2 (DE-588)4214982-4 |
| title | Verification techniques for system-level design |
| title_auth | Verification techniques for system-level design |
| title_exact_search | Verification techniques for system-level design |
| title_full | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_fullStr | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_full_unstemmed | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_short | Verification techniques for system-level design |
| title_sort | verification techniques for system level design |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Formal methods (Computer science) fast Integrated circuits / Verification fast Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated TECHNOLOGY & ENGINEERING / Electronics / Circuits / General Systems on a chip / Testing Integrated circuits / Verification Formal methods (Computer science) Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip LSI Hardwareverifikation |
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