VLSI test principles and architectures: design for testability
Gespeichert in:
| Weitere Verfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam ; Boston
Elsevier Morgan Kaufmann Publishers
2006
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Beschreibung: | Print version record |
| Beschreibung: | 1 online resource (xxx, 777 pages) illustrations |
| ISBN: | 9780080474793 0080474799 |
Internformat
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| 245 | 1 | 0 | |a VLSI test principles and architectures |b design for testability |c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
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| 505 | 8 | |a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website | |
| 650 | 4 | |a Circuits integres a tres grande echelle / Essais | |
| 650 | 4 | |a Circuits integres a tres grande echelle / Conception et construction | |
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| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic |2 bisacsh | |
| 650 | 7 | |a COMPUTERS / Logic Design |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Testing |2 blmlsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design |2 blmlsh | |
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Datensatz im Suchindex
| _version_ | 1804179159150231552 |
|---|---|
| any_adam_object | |
| author2 | Wang, Laung-Terng Wen, Xiaoqing |
| author2_role | edt edt |
| author2_variant | l t w ltw x w xw |
| author_facet | Wang, Laung-Terng Wen, Xiaoqing |
| building | Verbundindex |
| bvnumber | BV045341931 |
| collection | ZDB-4-ENC |
| contents | This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website |
| ctrlnum | (ZDB-4-ENC)ocn162573568 (OCoLC)162573568 (DE-599)BVBBV045341931 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV045341931 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:26Z |
| institution | BVB |
| isbn | 9780080474793 0080474799 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030728634 |
| oclc_num | 162573568 |
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| physical | 1 online resource (xxx, 777 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2006 |
| publishDateSearch | 2006 |
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| publisher | Elsevier Morgan Kaufmann Publishers |
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| spelling | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen Amsterdam ; Boston Elsevier Morgan Kaufmann Publishers 2006 1 online resource (xxx, 777 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Print version record This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website Circuits integres a tres grande echelle / Essais Circuits integres a tres grande echelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Testen (DE-588)4367264-4 s 1\p DE-604 Wang, Laung-Terng edt Wu, Cheng-Wen Sonstige oth Wen, Xiaoqing edt Erscheint auch als Druck-Ausgabe VLSI test principles and architectures Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, 2006 0123705975 9780123705976 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | VLSI test principles and architectures design for testability This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website Circuits integres a tres grande echelle / Essais Circuits integres a tres grande echelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4367264-4 (DE-588)4117388-0 |
| title | VLSI test principles and architectures design for testability |
| title_auth | VLSI test principles and architectures design for testability |
| title_exact_search | VLSI test principles and architectures design for testability |
| title_full | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_fullStr | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_full_unstemmed | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_short | VLSI test principles and architectures |
| title_sort | vlsi test principles and architectures design for testability |
| title_sub | design for testability |
| topic | Circuits integres a tres grande echelle / Essais Circuits integres a tres grande echelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Testen gnd VLSI gnd Circuitos integrados vlsi larpcal Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Circuits integres a tres grande echelle / Essais Circuits integres a tres grande echelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Testen VLSI Circuitos integrados vlsi Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design |
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