ASIC and FPGA verification: a guide to component modeling
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Francisco, Calif.
Morgan Kaufmann
2005
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Beschreibung: | Includes index Print version record |
| Beschreibung: | 1 online resource (1 volume) |
| ISBN: | 1417549718 9781417549719 9780125105811 0125105819 9780080475929 0080475922 |
Internformat
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| 100 | 1 | |a Munden, Richard |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a ASIC and FPGA verification |b a guide to component modeling |c Richard Munden |
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| 505 | 8 | |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification | |
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Datensatz im Suchindex
| _version_ | 1804179157496627200 |
|---|---|
| any_adam_object | |
| author | Munden, Richard |
| author_facet | Munden, Richard |
| author_role | aut |
| author_sort | Munden, Richard |
| author_variant | r m rm |
| building | Verbundindex |
| bvnumber | BV045341129 |
| collection | ZDB-4-ENC |
| contents | Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification |
| ctrlnum | (ZDB-4-ENC)ocm56837419 (OCoLC)56837419 (DE-599)BVBBV045341129 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV045341129 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:15:24Z |
| institution | BVB |
| isbn | 1417549718 9781417549719 9780125105811 0125105819 9780080475929 0080475922 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030727833 |
| oclc_num | 56837419 |
| open_access_boolean | |
| physical | 1 online resource (1 volume) |
| psigel | ZDB-4-ENC |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Morgan Kaufmann |
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| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Munden, Richard Verfasser aut ASIC and FPGA verification a guide to component modeling Richard Munden San Francisco, Calif. Morgan Kaufmann 2005 1 online resource (1 volume) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes index Print version record Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification Circuits integres a la demande Reseaux logiques programmables par l'utilisateur TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application specific integrated circuits cct Application-specific integrated circuits fast Application-specific integrated circuits Verifikation (DE-588)4135577-5 gnd rswk-swf Hierarchische Simulation (DE-588)4426470-7 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Field programmable gate array (DE-588)4347749-5 s Hierarchische Simulation (DE-588)4426470-7 s 1\p DE-604 Digitalelektronik (DE-588)4260328-6 s Integrierte Schaltung (DE-588)4027242-4 s Verifikation (DE-588)4135577-5 s 2\p DE-604 Erscheint auch als Druck-Ausgabe Munden, Richard ASIC and FPGA verification San Francisco, Calif. : Morgan Kaufmann, 2005 0125105819 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Munden, Richard ASIC and FPGA verification a guide to component modeling Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification Circuits integres a la demande Reseaux logiques programmables par l'utilisateur TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application specific integrated circuits cct Application-specific integrated circuits fast Application-specific integrated circuits Verifikation (DE-588)4135577-5 gnd Hierarchische Simulation (DE-588)4426470-7 gnd Field programmable gate array (DE-588)4347749-5 gnd Digitalelektronik (DE-588)4260328-6 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4135577-5 (DE-588)4426470-7 (DE-588)4347749-5 (DE-588)4260328-6 (DE-588)4122250-7 (DE-588)4027242-4 |
| title | ASIC and FPGA verification a guide to component modeling |
| title_auth | ASIC and FPGA verification a guide to component modeling |
| title_exact_search | ASIC and FPGA verification a guide to component modeling |
| title_full | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_fullStr | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_full_unstemmed | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_short | ASIC and FPGA verification |
| title_sort | asic and fpga verification a guide to component modeling |
| title_sub | a guide to component modeling |
| topic | Circuits integres a la demande Reseaux logiques programmables par l'utilisateur TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application specific integrated circuits cct Application-specific integrated circuits fast Application-specific integrated circuits Verifikation (DE-588)4135577-5 gnd Hierarchische Simulation (DE-588)4426470-7 gnd Field programmable gate array (DE-588)4347749-5 gnd Digitalelektronik (DE-588)4260328-6 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Circuits integres a la demande Reseaux logiques programmables par l'utilisateur TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Application specific integrated circuits Application-specific integrated circuits Verifikation Hierarchische Simulation Field programmable gate array Digitalelektronik Kundenspezifische Schaltung Integrierte Schaltung |
| work_keys_str_mv | AT mundenrichard asicandfpgaverificationaguidetocomponentmodeling |