RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tualatin, Oregon, USA
Sutherland HDL, Inc.
[2017]
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | xxxi, 453 Seiten Illustrationen, Diagramme |
| ISBN: | 9781546776345 1546776346 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV045314201 | ||
| 003 | DE-604 | ||
| 005 | 20231205 | ||
| 007 | t | ||
| 008 | 181127s2017 a||| |||| 00||| eng d | ||
| 020 | |a 9781546776345 |c Broschur |9 978-1-5467-7634-5 | ||
| 020 | |a 1546776346 |9 1-5467-7634-6 | ||
| 035 | |a (OCoLC)1015870870 | ||
| 035 | |a (DE-599)BSZ495775835 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-862 | ||
| 050 | 0 | |a TK7885.7 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 100 | 1 | |a Sutherland, Stuart |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |c Stuart Sutherland |
| 264 | 1 | |a Tualatin, Oregon, USA |b Sutherland HDL, Inc. |c [2017] | |
| 300 | |a xxxi, 453 Seiten |b Illustrationen, Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 653 | 0 | |a Verilog (Computer hardware description language) | |
| 653 | 0 | |a Electronic digital computers / Design and construction | |
| 653 | 0 | |a Computer simulation | |
| 653 | 0 | |a Computer simulation | |
| 653 | 0 | |a Electronic digital computers / Design and construction | |
| 653 | 0 | |a Verilog (Computer hardware description language) | |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | 1 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 0 | 2 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030701167 | ||
Datensatz im Suchindex
| DE-BY-862_location | 2000 |
|---|---|
| DE-BY-FWS_call_number | 2000/ZN 4904 S966 |
| DE-BY-FWS_katkey | 709175 |
| DE-BY-FWS_media_number | 083000520943 083000525583 |
| _version_ | 1824553613027966976 |
| any_adam_object | |
| author | Sutherland, Stuart |
| author_facet | Sutherland, Stuart |
| author_role | aut |
| author_sort | Sutherland, Stuart |
| author_variant | s s ss |
| building | Verbundindex |
| bvnumber | BV045314201 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 ZN 4904 |
| ctrlnum | (OCoLC)1015870870 (DE-599)BSZ495775835 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV045314201 |
| illustrated | Illustrated |
| indexdate | 2025-02-20T06:38:39Z |
| institution | BVB |
| isbn | 9781546776345 1546776346 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030701167 |
| oclc_num | 1015870870 |
| open_access_boolean | |
| owner | DE-862 DE-BY-FWS |
| owner_facet | DE-862 DE-BY-FWS |
| physical | xxxi, 453 Seiten Illustrationen, Diagramme |
| publishDate | 2017 |
| publishDateSearch | 2017 |
| publishDateSort | 2017 |
| publisher | Sutherland HDL, Inc. |
| record_format | marc |
| spellingShingle | Sutherland, Stuart RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design Field programmable gate array (DE-588)4347749-5 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4122250-7 (DE-588)4268385-3 |
| title | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |
| title_auth | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |
| title_exact_search | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |
| title_full | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design Stuart Sutherland |
| title_fullStr | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design Stuart Sutherland |
| title_full_unstemmed | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design Stuart Sutherland |
| title_short | RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design |
| title_sort | rtl modeling with systemverilog for simulation and synthesis using systemverilog for asic and fpga design |
| topic | Field programmable gate array (DE-588)4347749-5 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Field programmable gate array Kundenspezifische Schaltung VERILOG |
| work_keys_str_mv | AT sutherlandstuart rtlmodelingwithsystemverilogforsimulationandsynthesisusingsystemverilogforasicandfpgadesign |