APA (7th ed.) Citation

Thomas, D. B. (2016). Logic design and verification using SystemVerilog (Revised.). Donald Thomas.

Chicago Style (17th ed.) Citation

Thomas, Donald B. Logic Design and Verification Using SystemVerilog. Revised. Pittsburgh, PA: Donald Thomas, 2016.

MLA (9th ed.) Citation

Thomas, Donald B. Logic Design and Verification Using SystemVerilog. Revised. Donald Thomas, 2016.

Warning: These citations may not always be 100% accurate.