Digital design: with an introduction to the Verilog HDL, VHDL, and SystemVerilog
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Pearson
[2019]
|
| Ausgabe: | Sixth edition, global edition |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 710 Seiten Illustrationen, Diagramme |
| ISBN: | 9781292231167 1292231165 |
Internformat
MARC
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| 245 | 1 | 0 | |a Digital design |b with an introduction to the Verilog HDL, VHDL, and SystemVerilog |c M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs |
| 250 | |a Sixth edition, global edition | ||
| 264 | 1 | |a New York, NY |b Pearson |c [2019] | |
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Datensatz im Suchindex
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| adam_text | Contents Preface 1 Digi¡tal Systems and Binary Numbers 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 9 Digital Systems Binary Numbers Number-Base Conversions Octal and Hexadecimal Numbers Complements of Numbers Signed Binary Numbers Binary Codes Binary Storage and Registers Binary Logic 77 77 20 22 25 27 33 38 47 SO Boo lean Algebra and Logic Gates 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Introduction Basic Definitions Axiomatic Definition of Boolean Algebra Basic Theorems and Properties of Boolean Algebra Boolean Functions Canonical and Standard Forms Other Logic Operations Digital Logic Gates Integrated Circuits 57 58 58 59 63 66 72 81 83 89 5
6 3 Contents Gate-Level Minimization 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 4 Introduction Combinational Circuits Analysis of Combinational Circuits Design Procedure Binary Adder-Subtractor Decimal Adder Binary Multiplier Magnitude Comparator Decoders Encoders Multiplexers HDL Models of Combinational Circuits Behavioral Modeling Writing a Simple Testbench Logic Simulation 163 164 164 165 169 172 184 186 188 191 195 198 205 231 239 245 Synchronous Sequential Logic 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6 99 99 106 111 115 118 126 131 137 154 Combinational Logic 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 5 Introduction The Map Method Four-Variable K-Map Product-of-Sums Simplification Don t-Care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Languages (HDLs) Truth Tables in HDLs 98 Introduction Sequential Circuits Storage Elements: Latches Storage Elements: Flip-Flops Analysis of Clocked Sequential Circuits Synthesizable HDL Models of Sequential Circuits State Reduction and Assignment Design Procedure 261 262 262 264 269 277 291 316 321 Registers and Counters 6.1 6.2 Registers Shift Registers 342 342 346
Contents 6.3 6.4 6.5 6.6 7 393 Introduction Random-Access Memory Memory Decoding Error Detection and Correction Read-Only Memory Programmable Logic Array Programmable Array Logic Sequential Programmable Devices 394 395 402 407 410 416 420 424 445 D e s i g n at the Register Transfer Level 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 9 354 359 367 372 Memory and Programmable Logic 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 Ripple Counters Synchronous Counters Other Counters HDL Models of Registers and Counters Introduction Register Transfer Level (RTL) Notation RTL Descriptions Algorithmic State Machines (ASMs) Design Example (ASMD CHART) HDL Description of Design Example Sequential Binary Multiplier Control Logic HDL Description of Binary Multiplier Design with Multiplexers Race-Free Design (Software Race Conditions) Latch-Free Design (Why Waste Silicon?) SystemVerilog—An Introduction 446 446 448 466 475 485 503 508 514 529 545 548 549 Laboratory Experiments with Standard ICs and FPGAs 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 Introduction to Experiments Experiment 1 : Binary and Decimal Numbers Experiment 2: Digital Logic Gates Experiment 3: Simplification of Boolean Functions Experiment 4: Combinational Circuits Experiment 5: Code Converters Experiment 6: Design with Multiplexers Experiment 7: Adders and Subtractors Experimente: Flip-Flops Experiment 9: Sequential Circuits Experiment 10: Counters 7 571 571 576 579 581 583 584 586 588 591 593 595
8 Contents 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 10 Experiment 11: Shift Registers Experiment 12: Serial Addition Experiment 13: Memory Unit Experiment 14: Lamp Handball Experiment 15: Clock-Pulse Generator Experiment 16: Parallel Adder and Accumulator Experiment 17: Binary Multiplier HDL Simulation Experiments and Rapid Prototyping with FPGAs 596 600 601 603 607 609 611 615 Standard Graphic Symbols 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Rectangular-Shape Symbols Qualifying Symbols Dependency Notation Symbols for Combinational Elements Symbols for Flip-Flops Symbols for Registers Symbols for Counters Symbol for RAM 62Ί 621 624 626 628 630 632 635 637 Appendix 640 Answers to Selected Problems 654 Index 699
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| any_adam_object | 1 |
| author | Mano, Moshe Morris 1927- Ciletti, Michael D. ca. 20./21. Jh |
| author_GND | (DE-588)172248078 (DE-588)1234031892 |
| author_facet | Mano, Moshe Morris 1927- Ciletti, Michael D. ca. 20./21. Jh |
| author_role | aut aut |
| author_sort | Mano, Moshe Morris 1927- |
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| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Sixth edition, global edition |
| format | Book |
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| id | DE-604.BV045276433 |
| illustrated | Illustrated |
| indexdate | 2025-02-20T06:43:18Z |
| institution | BVB |
| isbn | 9781292231167 1292231165 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030664100 |
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| physical | 710 Seiten Illustrationen, Diagramme |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
| publisher | Pearson |
| record_format | marc |
| spellingShingle | Mano, Moshe Morris 1927- Ciletti, Michael D. ca. 20./21. Jh Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog VERILOG (DE-588)4268385-3 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
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| title | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog |
| title_auth | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog |
| title_exact_search | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog |
| title_full | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs |
| title_fullStr | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs |
| title_full_unstemmed | Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog M. Morris Mano, Emeritus Professor of Computer Engineering, California State University, Los Angeles, Michael D. Ciletti, Emeritus Professor of Electrical and Computer Engineering, University of Colorado at Colorado Springs |
| title_short | Digital design |
| title_sort | digital design with an introduction to the verilog hdl vhdl and systemverilog |
| title_sub | with an introduction to the Verilog HDL, VHDL, and SystemVerilog |
| topic | VERILOG (DE-588)4268385-3 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | VERILOG Digitale integrierte Schaltung VHDL Digitalschaltung Schaltungsentwurf Logischer Entwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030664100&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT manomoshemorris digitaldesignwithanintroductiontotheveriloghdlvhdlandsystemverilog AT cilettimichaeld digitaldesignwithanintroductiontotheveriloghdlvhdlandsystemverilog |
Inhaltsverzeichnis
THWS Schweinfurt Zentralbibliothek Lesesaal
| Signatur: |
2000 ZN 4904 M285(6) |
|---|---|
| Exemplar 1 | ausleihbar Verfügbar Bestellen |