Holdings: Test Generation of Crosstalk Delay Faults in VLSI Circuits

Test Generation of Crosstalk Delay Faults in VLSI Circuits:

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Bibliographic Details
Main Authors:	Jayanthy, S. (Author), Bhuvaneswari, M.C (Author)
Format:	Electronic eBook
Language:	English
Published:	Singapore Springer Singapore 2019
Subjects:	Circuits and Systems Control Structures and Microprogramming Performance and Reliability Logic Design Systems engineering Microprogramming Operating systems (Computers) Logic design
Online Access:	BTU01 FAW01 FHA01 FHI01 FHM01 FHN01 FHR01 FKE01 FLA01 FRO01 FWS01 FWS02 HTW01 TUM01 UBA01 UBY01 Volltext
Physical Description:	1 Online-Ressource (XI, 156 p. 49 illus., 7 illus. in color)
ISBN:	9789811324932
DOI:	10.1007/978-981-13-2493-2

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Record in the Search Index

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illustrated	Not Illustrated
indexdate	2025-02-20T06:56:42Z
institution	BVB
isbn	9789811324932
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-030627698
oclc_num	1057679183
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owner	DE-384 DE-860 DE-91 DE-BY-TUM DE-1046 DE-Aug4 DE-898 DE-BY-UBR DE-861 DE-523 DE-859 DE-863 DE-BY-FWS DE-862 DE-BY-FWS DE-92 DE-573 DE-M347 DE-706 DE-634
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physical	1 Online-Ressource (XI, 156 p. 49 illus., 7 illus. in color)
psigel	ZDB-2-ENG ZDB-2-ENG_2019_Fremddaten
publishDate	2019
publishDateSearch	2019
publishDateSort	2019
publisher	Springer Singapore
record_format	marc
spellingShingle	Jayanthy, S. Bhuvaneswari, M.C Test Generation of Crosstalk Delay Faults in VLSI Circuits Circuits and Systems Control Structures and Microprogramming Performance and Reliability Logic Design Systems engineering Microprogramming Operating systems (Computers) Logic design
title	Test Generation of Crosstalk Delay Faults in VLSI Circuits
title_auth	Test Generation of Crosstalk Delay Faults in VLSI Circuits
title_exact_search	Test Generation of Crosstalk Delay Faults in VLSI Circuits
title_full	Test Generation of Crosstalk Delay Faults in VLSI Circuits by S. Jayanthy, M.C. Bhuvaneswari
title_fullStr	Test Generation of Crosstalk Delay Faults in VLSI Circuits by S. Jayanthy, M.C. Bhuvaneswari
title_full_unstemmed	Test Generation of Crosstalk Delay Faults in VLSI Circuits by S. Jayanthy, M.C. Bhuvaneswari
title_short	Test Generation of Crosstalk Delay Faults in VLSI Circuits
title_sort	test generation of crosstalk delay faults in vlsi circuits
topic	Circuits and Systems Control Structures and Microprogramming Performance and Reliability Logic Design Systems engineering Microprogramming Operating systems (Computers) Logic design
topic_facet	Circuits and Systems Control Structures and Microprogramming Performance and Reliability Logic Design Systems engineering Microprogramming Operating systems (Computers) Logic design
url	https://doi.org/10.1007/978-981-13-2493-2
work_keys_str_mv	AT jayanthys testgenerationofcrosstalkdelayfaultsinvlsicircuits AT bhuvaneswarimc testgenerationofcrosstalkdelayfaultsinvlsicircuits

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