Verilog HDL design examples:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boca Raton
CRC Press, Taylor & Francis Group
[2018]
|
| Schlagworte: | |
| Beschreibung: | xv, 655 Seiten Illustrationen |
| ISBN: | 9781138099951 |
Internformat
MARC
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| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030621791 | ||
Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Cavanagh, Joseph J. F. |
| author_facet | Cavanagh, Joseph J. F. |
| author_role | aut |
| author_sort | Cavanagh, Joseph J. F. |
| author_variant | j j f c jjf jjfc |
| building | Verbundindex |
| bvnumber | BV045233454 |
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| ctrlnum | (OCoLC)1077507308 (DE-599)BVBBV045233454 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV045233454 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:12:18Z |
| institution | BVB |
| isbn | 9781138099951 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030621791 |
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| owner | DE-83 |
| owner_facet | DE-83 |
| physical | xv, 655 Seiten Illustrationen |
| publishDate | 2018 |
| publishDateSearch | 2018 |
| publishDateSort | 2018 |
| publisher | CRC Press, Taylor & Francis Group |
| record_format | marc |
| spelling | Cavanagh, Joseph J. F. Verfasser aut Verilog HDL design examples Joseph Cavanagh Boca Raton CRC Press, Taylor & Francis Group [2018] © 2018 xv, 655 Seiten Illustrationen txt rdacontent n rdamedia nc rdacarrier VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s DE-604 |
| spellingShingle | Cavanagh, Joseph J. F. Verilog HDL design examples VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4254792-1 |
| title | Verilog HDL design examples |
| title_auth | Verilog HDL design examples |
| title_exact_search | Verilog HDL design examples |
| title_full | Verilog HDL design examples Joseph Cavanagh |
| title_fullStr | Verilog HDL design examples Joseph Cavanagh |
| title_full_unstemmed | Verilog HDL design examples Joseph Cavanagh |
| title_short | Verilog HDL design examples |
| title_sort | verilog hdl design examples |
| topic | VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | VERILOG VHDL |
| work_keys_str_mv | AT cavanaghjosephjf veriloghdldesignexamples |