Introduction to digital systems design:
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cham
Springer
[2019]
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext http://www.springer.com/ Inhaltsverzeichnis |
| Beschreibung: | xxiii, 536 Seiten Illustrationen, Diagramme 23.5 cm x 15.5 cm |
| ISBN: | 9783319928036 3319928031 |
Internformat
MARC
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| 240 | 1 | 0 | |a Introduzione al Progetto di Sistemi Digitali |
| 245 | 1 | 0 | |a Introduction to digital systems design |c Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita |
| 264 | 1 | |a Cham |b Springer |c [2019] | |
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| 700 | 1 | |a Oneto, Luca |e Verfasser |4 aut | |
| 700 | 1 | |a Ponta, Domenico |e Verfasser |4 aut | |
| 700 | 1 | |a Anguita, Davide |e Verfasser |4 aut | |
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Datensatz im Suchindex
| _version_ | 1804178928920690688 |
|---|---|
| adam_text | Giuliano Donzellini • Luca Oneto
Domenico Ponta • Davide Anguita
Introduction to Digital
Systems Design
*0 Springer
Contents
1 Boolean Algebra and Combinational Logic 1
1 1 Analog and Discrete Variables 1
1 2 Boolean Variables 3
1 3 Boolean Functions 4
1 4 Truth Tables 4
1 5 Definition of Boolean Algebra 5
1 6 The Fundamental Properties of Boolean Algebra 6
1 7 Other Operations 10
1 8 Functionally Complete Operation Sets 11
1 9 Shannon’s Expansion Theorem 14
1 10 Level of Boolean Expressions 17
1 11 Literals 17
1 12 Minterms 18
1 13 Maxterms 18
1 14 Implicants 18
1 15 Prime Implicants 18
1 16 Combinational Networks 19
1 16 1 Example: Logical Network Analysis 19
1 16 2 Example: Two-Level Logical Network Analysis 20
1 16 3 Example: Circuit Schematic of a Logical
Network (1) 20
1 16 4 Example: Circuit Schematic of a Logical
Network (2) 21
1 16 5 Example: Defining the Behavior of a Logical
Network 21
1 16 6 Example: Circuit Schematic from the Truth Table 22
1 16 7 Example: Controlling a Heating System 23
1 16 8 Example: Two Channels Multiplexer (Selector) 24
xvii
xviii Contents
1 17 Exercises 27
1 18 Solutions 29
2 Combinational Network Design 23
2 1 Karnaugh Maps 33
2 2 Using Maps for AND-OR Synthesis 36
221 Implicants and Prime Implicants in Karnaugh Maps 38
222 Using Maps for Minimization 41
223 “Checkerboard” Maps 41
224 Examples of AND-OR Synthesis 42
2 3 OR-AND Synthesis 45
231 Synthesis of the Negated Function 46
2 4 NAND-NAND Synthesis 46
2 5 NOR-NOR Synthesis 47
2 6 Standard Combinational Networks 48
261 Decoders 48
262 Multiplexer 51
263 Demultiplexers 53
264 Seven-Segment Display Decoder 55
265 Seven-Segment BCD Decoder (using “don’t-cares”) 57
266 Using Multiplexers to Synthesize Combinational
Networks 58
2 7 Variable-Entered Maps 60
271 Synthesizing Maps with Entered Variables 60
272 Entered Variables and Theorems of Expansion 63
2 8 Time Behavior of Combinational Networks 64
281 Definitions and Timing Models 64
282 Hazards 66
283 Elimination of Static Hazards 67
284 Notes on Eliminating Hazards 70
2 9 Exercises 70
291 Maps 70
292 Hazards 72
2 10 Solutions 73
2 10 1 Maps 73
2 10 2 Hazards 77
3 Numeral Systems and Binary Arithmetic 79
3 1 Binary Information 79
3 2 Binary Numbering System (BIN) 80
321 Converting from Binary System to Decimal 80
322 Converting from Decimal System to Binary 81
323 Maximum Representable Number 82
3 3 Octal Number System (OCT) 83
Contents xix
3 4 Hexadecimal Number System (HEX) 84
3 5 Others Binary Codes 85
351 Binary Coded Decimal 85
352 GRAY Codes 86
3 6 Binary Arithmetic 87
361 Addition 87
362 Subtraction 88
363 Products 89
3 7 BCD 8421 Arithmetic 89
3 8 Binary Rational Numbers 91
3 9 Arithmetic Networks 91
391 Half Adders 91
392 Full Adders 92
393 Ripple Carry Adder 93
394 Arithmetic Logic Unit (ALU) 94
3 10 Relative Numbers in Binary 95
3 10 1 Representation in “Module and Sign” Code 95
3 10 2 Complementation 97
3 10 3 Representation in “Ones’Complement” Code 99
3 10 4 Representation in “Two’s Complement” Code 101
3 10 5 Sign Extension 102
3 11 Representation of Real Numbers 103
3 12 Alphanumeric Codes 104
3 13 Error Detection Codes: Parity Generator and Checker 106
3 14 Exercises 108
3 14 1 Binary Numbers 108
3 14 2 Signed Binary Numbers 108
3 14 3 Octal and Hexadecimal Numbers 109
3 15 Solutions 109
3 15 1 Binary Numbers 109
3 15 2 Signed Binary Numbers 111
3 15 3 Octal and Hexadecimal Numbers 112
4 Complements in Combinational Network Design 115
4 1 Minimizing Boolean Expressions with the Quine-McCluskey
Method 115
411 The Expansion Phase 116
412 The Covering Phase 119
413 Incompletely Specified Functions 120
414 Optimizing the Covering Phase 120
415 Simultaneous Optimization of Multiple Functions 125
XX
Contents
4 2 Exercises 130
421 Quine-McCluskey: Single Function Synthesis 130
422 Quine-McCluskey: Jointly Synthesis of Multiple
Functions 133
4 3 Solutions 136
431 Quine-McCluskey: Synthesis of a Single Function 136
432 Quine-McCluskey: Joint Synthesis of Multiple
Functions 137
5 Introduction to Sequential Networks 139
5 1 From Combinational Networks to Sequential Networks 139
511 Introductory Example 140
512 Memorizing an Information Bit: Flip-Flops 141
513 Flip-Flop Classification: Logical Type and Command
Type 142
5 2 Direct Command Flip-Flops 143
521 SR Flip-Flop 143
522D Flip-Flop 147
523 JK Flip-Flop 148
5 3 Initialization of a Sequential Network 149
531 Flip-Flop Initialization Inputs 150
532 Generating an Initialization Signal 152
5 4 Level-Enabled Flip-Flops 153
541 SR-Latch Flip-Hop 153
542 D-Latch Hip-Hop 155
543 JK-Latch Hip-Flop 156
5 5 Synchronization of Sequential Networks 157
551 The Synchronization Signal 157
552 Pulse Command in Level-Enabled Flip-Flops 158
553 The “Clock” and the “Edge-Triggered Command” 159
554 Master-Slave Structure 160
5 6 Edge-Triggered Hip-Flops 162
561 D-PET Hip-Hop 162
562 E-PET Hip-Flop 166
563 JK-PET Hip-Flop 168
564 T-PET Hip-Hop 170
565 Synchronous Initialization of Hip-Hops 171
5 7 Timing Parameters of Hip-Hops 171
571 Relationship Between Propagation and Hold Times 172
572 Maximum Clock Frequency of a Network
with Hip-Flops 173
5 8 Hip-Hops: Graphic Symbols and Tables 174
581 Logical Types 174
Contents
xxi
582 Command Types 175
583 Excitation Tables 177
5 9 Exercises 178
5 10 Solutions 181
6 Flip-Flop-Based Synchronous Networks 183
6 1 Synchronous and Asynchronous Signals 185
611 Synchronizer 186
612 Multistage Synchronization 187
6 2 Registers 188
621 Parallel Registers 188
622 Shift Registers 190
623 Shift Registers with Parallel Load 193
624 Universal Shift Register 196
6 3 Counters 199
631 Binary Counters 199
632 Counters with Enabling 205
633 Up/Down Counters 207
634 “Universal” Counters 210
635 Asynchronous Counters 213
6 4 Network Analysis Examples 215
641 Example 1 215
642 Example 2 218
643 Example 3 221
644 Example 4 223
645 Example 5 224
6 5 Exercises 228
6 6 Solutions 248
7 Sequential Networks as Finite State Machines 259
7 1 Finite State Machines: Standard Model 260
711 Synchronous and Asynchronous Machines 261
712 Moore and Mealy Machines 261
713 An Example of Synchronous Finite State Machine 262
714 General Equations of the Next State and the Outputs 263
7 2 ASM Diagrams 265
721 Description of States 265
722 Inputs 269
723 Conditional Outputs 277
7 3 Examples of ASM Diagram Construction 282
731 Introductory Examples 282
732 Pulse Generators with Adjustable Duty Cycle 291
733 Sequence Detector 296
734 Serial Synchronous Transmitters (2 bits) 298
xxii Contents
735 Command Receiver with Serial Synchronous
Interface 300
736 Serial Synchronous Receiver (2 bits) 303
737 Push-Button Handling 306
738 3-Bit Shift Registers 309
739 Sequential Networks with Conditional Outputs 31
7 3 10 Shift Register with XOR Tree 31
7 4 Synthesis of Synchronous FSM 31
741 State Assignment 31
742 Describing an FSM with a State Table 31
743 State Table Synthesis 32
744 Examples of Synchronous FSM Synthesis 32
7 5 Time Behavior of Synchronous FSM 33
751 FSM with no Inputs 33
752 FSM with Synchronous and Asynchronous Inputs 33
753 Synchronous Inputs 34
754 Asynchronous Inputs 341
755 FSM Outputs (Moore’s Model) 34
756 FSM Outputs (Mealy’s Model) 34
7 6 Exercises 34
761 Sequential Network Analysis in Terms of FSMs 34
762 FSM Design Based on Textual Specifications 34
7 7 Solutions 35
771 Sequential Network Analysis in Terms of FSMs 35
772 FSM Design Based on Textual Specifications 35
8 The Finite State Machine as System Controller 36
8 1 Digital Systems 36
8 2 Open Control Systems 3
821 2-Bit Serial Receiver 36
8 3 Feedback Control Systems 36
831 2-Bit Serial Receiver and Transmitter 36
832 Pulse Generator 37
833 8-Bit Serial Receiver 37
834 Light Dimmer 3
835 Combination Lock 38
836 Automatic Drink Dispenser 39
837 Programmable Square Wave Generator 39
838 Christmas Light Systems 40
8 4 Design Exercises 40
841 Design of the Controller of a Given Datapath 40
842 Design of a Controller-Datapath System 42
Contents xxiii
8 5 Design Tips 427
851 Design of a Controller-Datapath System 427
8 6 Solutions 434
861 Design of the Controller of a Given Datapath 434
862 Design of a Controller-Datapath System 452
9 Introduction to FPGA and HDL Design 465
9 1 Field-Programmable Gate Arrays 465
911 System Prototyping and FPGA 466
912 FPGA Board Examples 467
913 FPGA Architecture 470
914 JTAG Programming 472
915 FPGA Development Tools 475
916 Deeds Support for FPGA 478
9 2 Introduction to VHDL 485
921 VHDL Code from Deeds 486
922 Counter 487
923 Finite State Machine 491
924 Top-Level Entity 494
925 Other VHDL Examples 497
9 3 FPGA Prototyping Exercises 506
931 Synchronous Serial Communication System (8-bit) 506
932 Digital Chronometer 510
9 4 Solutions 514
941 Synchronous Serial Communication System (8-bit) 514
942 Digital Chronometer 515
Appendix A: The Powers of 2 519
Appendix B: State Diagrams 521
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| spelling | Donzellini, Giuliano Verfasser aut Introduzione al Progetto di Sistemi Digitali Introduction to digital systems design Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita Cham Springer [2019] © 2019 xxiii, 536 Seiten Illustrationen, Diagramme 23.5 cm x 15.5 cm txt rdacontent n rdamedia nc rdacarrier Computer (DE-588)4070083-5 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf THR UYF Algorithmus (DE-588)4001183-5 s Computer (DE-588)4070083-5 s DE-604 Oneto, Luca Verfasser aut Ponta, Domenico Verfasser aut Anguita, Davide Verfasser aut Springer International Publishing (DE-588)1064344704 pbl Erscheint auch als Online-Ausgabe 978-3-319-92804-3 X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=f80add21267e42c8b14b597c8282c6a9&prov=M&dok_var=1&dok_ext=htm Inhaltstext X:MVB http://www.springer.com/ HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030603548&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Donzellini, Giuliano Oneto, Luca Ponta, Domenico Anguita, Davide Introduction to digital systems design Computer (DE-588)4070083-5 gnd Algorithmus (DE-588)4001183-5 gnd |
| subject_GND | (DE-588)4070083-5 (DE-588)4001183-5 |
| title | Introduction to digital systems design |
| title_alt | Introduzione al Progetto di Sistemi Digitali |
| title_auth | Introduction to digital systems design |
| title_exact_search | Introduction to digital systems design |
| title_full | Introduction to digital systems design Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita |
| title_fullStr | Introduction to digital systems design Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita |
| title_full_unstemmed | Introduction to digital systems design Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita |
| title_short | Introduction to digital systems design |
| title_sort | introduction to digital systems design |
| topic | Computer (DE-588)4070083-5 gnd Algorithmus (DE-588)4001183-5 gnd |
| topic_facet | Computer Algorithmus |
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