Matrix Computations on Systolic-Type Arrays:
Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth,...
Gespeichert in:
Hauptverfasser: | , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1992
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Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science
174 |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage. Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives. Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer |
Beschreibung: | 1 Online-Ressource (XXVII, 280 p) |
ISBN: | 9781461536109 |
DOI: | 10.1007/978-1-4615-3610-9 |
Internformat
MARC
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490 | 0 | |a The Kluwer International Series in Engineering and Computer Science |v 174 | |
520 | |a Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage. Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives. Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer | ||
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Datensatz im Suchindex
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any_adam_object | |
author | Moreno, Jaime H. Lang, Tomás |
author_facet | Moreno, Jaime H. Lang, Tomás |
author_role | aut aut |
author_sort | Moreno, Jaime H. |
author_variant | j h m jh jhm t l tl |
building | Verbundindex |
bvnumber | BV045187927 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4615-3610-9 (OCoLC)1053825632 (DE-599)BVBBV045187927 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4615-3610-9 |
format | Electronic eBook |
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id | DE-604.BV045187927 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:11:00Z |
institution | BVB |
isbn | 9781461536109 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030577104 |
oclc_num | 1053825632 |
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owner_facet | DE-634 |
physical | 1 Online-Ressource (XXVII, 280 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1992 |
publishDateSearch | 1992 |
publishDateSort | 1992 |
publisher | Springer US |
record_format | marc |
series2 | The Kluwer International Series in Engineering and Computer Science |
spelling | Moreno, Jaime H. Verfasser aut Matrix Computations on Systolic-Type Arrays by Jaime H. Moreno, Tomás Lang Boston, MA Springer US 1992 1 Online-Ressource (XXVII, 280 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science 174 Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage. Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives. Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Systolischer Algorithmus (DE-588)4224444-4 gnd rswk-swf Systolischer Algorithmus (DE-588)4224444-4 s 1\p DE-604 Lang, Tomás aut Erscheint auch als Druck-Ausgabe 9781461366041 https://doi.org/10.1007/978-1-4615-3610-9 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Moreno, Jaime H. Lang, Tomás Matrix Computations on Systolic-Type Arrays Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Systolischer Algorithmus (DE-588)4224444-4 gnd |
subject_GND | (DE-588)4224444-4 |
title | Matrix Computations on Systolic-Type Arrays |
title_auth | Matrix Computations on Systolic-Type Arrays |
title_exact_search | Matrix Computations on Systolic-Type Arrays |
title_full | Matrix Computations on Systolic-Type Arrays by Jaime H. Moreno, Tomás Lang |
title_fullStr | Matrix Computations on Systolic-Type Arrays by Jaime H. Moreno, Tomás Lang |
title_full_unstemmed | Matrix Computations on Systolic-Type Arrays by Jaime H. Moreno, Tomás Lang |
title_short | Matrix Computations on Systolic-Type Arrays |
title_sort | matrix computations on systolic type arrays |
topic | Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Systolischer Algorithmus (DE-588)4224444-4 gnd |
topic_facet | Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Systolischer Algorithmus |
url | https://doi.org/10.1007/978-1-4615-3610-9 |
work_keys_str_mv | AT morenojaimeh matrixcomputationsonsystolictypearrays AT langtomas matrixcomputationsonsystolictypearrays |