Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench:
Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing...
Gespeichert in:
Hauptverfasser: | , , , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1990
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Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
85 |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design) |
Beschreibung: | 1 Online-Ressource (XIV, 306 p) |
ISBN: | 9781461315193 |
DOI: | 10.1007/978-1-4613-1519-3 |
Internformat
MARC
LEADER | 00000nmm a2200000zcb4500 | ||
---|---|---|---|
001 | BV045187859 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180912s1990 |||| o||u| ||||||eng d | ||
020 | |a 9781461315193 |9 978-1-4613-1519-3 | ||
024 | 7 | |a 10.1007/978-1-4613-1519-3 |2 doi | |
035 | |a (ZDB-2-ENG)978-1-4613-1519-3 | ||
035 | |a (OCoLC)1184434328 | ||
035 | |a (DE-599)BVBBV045187859 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-634 | ||
082 | 0 | |a 621.3815 |2 23 | |
100 | 1 | |a Thomas, D. E. |e Verfasser |4 aut | |
245 | 1 | 0 | |a Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench |c by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn |
264 | 1 | |a Boston, MA |b Springer US |c 1990 | |
300 | |a 1 Online-Ressource (XIV, 306 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
490 | 0 | |a The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 85 | |
520 | |a Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design) | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
650 | 4 | |a Engineering | |
650 | 4 | |a Computer-aided engineering | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
689 | 1 | 0 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |D s |
689 | 1 | |8 2\p |5 DE-604 | |
700 | 1 | |a Lagnese, E. D. |4 aut | |
700 | 1 | |a Walker, R. A. |4 aut | |
700 | 1 | |a Nestor, J. A. |4 aut | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461288152 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4613-1519-3 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_Archiv | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030577036 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/978-1-4613-1519-3 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178880465993728 |
---|---|
any_adam_object | |
author | Thomas, D. E. Lagnese, E. D. Walker, R. A. Nestor, J. A. |
author_facet | Thomas, D. E. Lagnese, E. D. Walker, R. A. Nestor, J. A. |
author_role | aut aut aut aut |
author_sort | Thomas, D. E. |
author_variant | d e t de det e d l ed edl r a w ra raw j a n ja jan |
building | Verbundindex |
bvnumber | BV045187859 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4613-1519-3 (OCoLC)1184434328 (DE-599)BVBBV045187859 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4613-1519-3 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03970nmm a2200625zcb4500</leader><controlfield tag="001">BV045187859</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1990 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461315193</subfield><subfield code="9">978-1-4613-1519-3</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4613-1519-3</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4613-1519-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184434328</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045187859</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Thomas, D. E.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench</subfield><subfield code="c">by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XIV, 306 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="v">85</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Register-Transfer-Ebene</subfield><subfield code="0">(DE-588)4215789-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Register-Transfer-Ebene</subfield><subfield code="0">(DE-588)4215789-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lagnese, E. D.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Walker, R. A.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Nestor, J. A.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461288152</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4613-1519-3</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030577036</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4613-1519-3</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV045187859 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:11:00Z |
institution | BVB |
isbn | 9781461315193 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030577036 |
oclc_num | 1184434328 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XIV, 306 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1990 |
publishDateSearch | 1990 |
publishDateSort | 1990 |
publisher | Springer US |
record_format | marc |
series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
spelling | Thomas, D. E. Verfasser aut Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn Boston, MA Springer US 1990 1 Online-Ressource (XIV, 306 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 85 Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design) Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Entwurf (DE-588)4121208-3 s 1\p DE-604 Register-Transfer-Ebene (DE-588)4215789-4 s 2\p DE-604 Lagnese, E. D. aut Walker, R. A. aut Nestor, J. A. aut Erscheint auch als Druck-Ausgabe 9781461288152 https://doi.org/10.1007/978-1-4613-1519-3 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Thomas, D. E. Lagnese, E. D. Walker, R. A. Nestor, J. A. Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd Register-Transfer-Ebene (DE-588)4215789-4 gnd Entwurf (DE-588)4121208-3 gnd |
subject_GND | (DE-588)4027242-4 (DE-588)4215789-4 (DE-588)4121208-3 |
title | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench |
title_auth | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench |
title_exact_search | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench |
title_full | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn |
title_fullStr | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn |
title_full_unstemmed | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench by D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn |
title_short | Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench |
title_sort | algorithmic and register transfer level synthesis the system architect s workbench |
topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd Register-Transfer-Ebene (DE-588)4215789-4 gnd Entwurf (DE-588)4121208-3 gnd |
topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Integrierte Schaltung Register-Transfer-Ebene Entwurf |
url | https://doi.org/10.1007/978-1-4613-1519-3 |
work_keys_str_mv | AT thomasde algorithmicandregistertransferlevelsynthesisthesystemarchitectsworkbench AT lagneseed algorithmicandregistertransferlevelsynthesisthesystemarchitectsworkbench AT walkerra algorithmicandregistertransferlevelsynthesisthesystemarchitectsworkbench AT nestorja algorithmicandregistertransferlevelsynthesisthesystemarchitectsworkbench |