High Level Synthesis of ASICs under Timing and Synchronization Constraints:
Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in th...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1992
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
177 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis |
| Beschreibung: | 1 Online-Ressource (XIV, 294 p) |
| ISBN: | 9781475721171 |
| DOI: | 10.1007/978-1-4757-2117-1 |
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| 520 | |a Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis | ||
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| spelling | Ku, David C. Verfasser aut High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku, Giovanni De Micheli Boston, MA Springer US 1992 1 Online-Ressource (XIV, 294 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 177 Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Schaltungsentwurf (DE-588)4179389-4 s 1\p DE-604 Micheli, Giovanni De aut Erscheint auch als Druck-Ausgabe 9781441951298 https://doi.org/10.1007/978-1-4757-2117-1 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Ku, David C. Micheli, Giovanni De High Level Synthesis of ASICs under Timing and Synchronization Constraints Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltungsentwurf (DE-588)4179389-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4122250-7 |
| title | High Level Synthesis of ASICs under Timing and Synchronization Constraints |
| title_auth | High Level Synthesis of ASICs under Timing and Synchronization Constraints |
| title_exact_search | High Level Synthesis of ASICs under Timing and Synchronization Constraints |
| title_full | High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku, Giovanni De Micheli |
| title_fullStr | High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku, Giovanni De Micheli |
| title_full_unstemmed | High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku, Giovanni De Micheli |
| title_short | High Level Synthesis of ASICs under Timing and Synchronization Constraints |
| title_sort | high level synthesis of asics under timing and synchronization constraints |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltungsentwurf (DE-588)4179389-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltungsentwurf Kundenspezifische Schaltung |
| url | https://doi.org/10.1007/978-1-4757-2117-1 |
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