Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...

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Bibliographische Detailangaben

Hauptverfasser:	Hachtel, Gary D. (VerfasserIn), Somenzi, Fabio (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1996
Schlagworte:	Engineering Circuits and Systems Logics and Meanings of Programs Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Discrete Mathematics in Computer Science Computing Methodologies Computer logic Computer science / Mathematics Computers Computer-aided engineering Electrical engineering Electronic circuits Logiksynthese Logischer Entwurf
Online-Zugang:	BTU01 UPA01 URL des Erstveröffentlichers
Zusammenfassung:	Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs
Beschreibung:	1 Online-Ressource (XXXII, 564 p)
ISBN:	9780306475924
DOI:	10.1007/b117060