Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to r...

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Bibliographische Detailangaben

Hauptverfasser:	Umamageswaran, Kothanda (VerfasserIn), Pandey, Sheetanshu L. (VerfasserIn), Wilsey, Philip A. (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1999
Schlagworte:	Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits
Online-Zugang:	BTU01 Volltext
Zusammenfassung:	Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
Beschreibung:	1 Online-Ressource (XXI, 158 p)
ISBN:	9781461551232
DOI:	10.1007/978-1-4615-5123-2