APA-Zitierstil (7. Ausg.)

Rao, V. B., Overhauser, D. V., Trick, T. N., & Hajj, I. N. (1989). Switch-Level Timing Simulation of MOS VLSI Circuits. Springer US. https://doi.org/10.1007/978-1-4613-1709-8

Chicago-Zitierstil (17. Ausg.)

Rao, Vasant B., David V. Overhauser, Timothy N. Trick, und Ibrahim N. Hajj. Switch-Level Timing Simulation of MOS VLSI Circuits. Boston, MA: Springer US, 1989. https://doi.org/10.1007/978-1-4613-1709-8.

MLA-Zitierstil (9. Ausg.)

Rao, Vasant B., et al. Switch-Level Timing Simulation of MOS VLSI Circuits. Springer US, 1989. https://doi.org/10.1007/978-1-4613-1709-8.