Switch-Level Timing Simulation of MOS VLSI Circuits:
Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly,...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1989
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
66 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation |
| Beschreibung: | 1 Online-Ressource (XII, 210 p) |
| ISBN: | 9781461317098 |
| DOI: | 10.1007/978-1-4613-1709-8 |
Internformat
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Datensatz im Suchindex
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| author | Rao, Vasant B. Overhauser, David V. Trick, Timothy N. Hajj, Ibrahim N. |
| author_facet | Rao, Vasant B. Overhauser, David V. Trick, Timothy N. Hajj, Ibrahim N. |
| author_role | aut aut aut aut |
| author_sort | Rao, Vasant B. |
| author_variant | v b r vb vbr d v o dv dvo t n t tn tnt i n h in inh |
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| bvnumber | BV045187340 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4613-1709-8 (OCoLC)1053814009 (DE-599)BVBBV045187340 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4613-1709-8 |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:59Z |
| institution | BVB |
| isbn | 9781461317098 |
| language | English |
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| physical | 1 Online-Ressource (XII, 210 p) |
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| publishDate | 1989 |
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| publisher | Springer US |
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| series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Rao, Vasant B. Verfasser aut Switch-Level Timing Simulation of MOS VLSI Circuits by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj Boston, MA Springer US 1989 1 Online-Ressource (XII, 210 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 66 Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Computersimulation (DE-588)4148259-1 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf MOS-Schaltung (DE-588)4135571-4 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf VLSI (DE-588)4117388-0 s MOS-Schaltung (DE-588)4135571-4 s Simulation (DE-588)4055072-2 s 1\p DE-604 Computersimulation (DE-588)4148259-1 s 2\p DE-604 Overhauser, David V. aut Trick, Timothy N. aut Hajj, Ibrahim N. aut Erscheint auch als Druck-Ausgabe 9781461289630 https://doi.org/10.1007/978-1-4613-1709-8 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Rao, Vasant B. Overhauser, David V. Trick, Timothy N. Hajj, Ibrahim N. Switch-Level Timing Simulation of MOS VLSI Circuits Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Computersimulation (DE-588)4148259-1 gnd VLSI (DE-588)4117388-0 gnd MOS-Schaltung (DE-588)4135571-4 gnd Simulation (DE-588)4055072-2 gnd |
| subject_GND | (DE-588)4148259-1 (DE-588)4117388-0 (DE-588)4135571-4 (DE-588)4055072-2 |
| title | Switch-Level Timing Simulation of MOS VLSI Circuits |
| title_auth | Switch-Level Timing Simulation of MOS VLSI Circuits |
| title_exact_search | Switch-Level Timing Simulation of MOS VLSI Circuits |
| title_full | Switch-Level Timing Simulation of MOS VLSI Circuits by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj |
| title_fullStr | Switch-Level Timing Simulation of MOS VLSI Circuits by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj |
| title_full_unstemmed | Switch-Level Timing Simulation of MOS VLSI Circuits by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj |
| title_short | Switch-Level Timing Simulation of MOS VLSI Circuits |
| title_sort | switch level timing simulation of mos vlsi circuits |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Computersimulation (DE-588)4148259-1 gnd VLSI (DE-588)4117388-0 gnd MOS-Schaltung (DE-588)4135571-4 gnd Simulation (DE-588)4055072-2 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Computersimulation VLSI MOS-Schaltung Simulation |
| url | https://doi.org/10.1007/978-1-4613-1709-8 |
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