VLSI Design for Manufacturing: Yield Enhancement:
One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1990
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
86 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book |
| Beschreibung: | 1 Online-Ressource (XII, 292 p) |
| ISBN: | 9781461315216 |
| DOI: | 10.1007/978-1-4613-1521-6 |
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| author | Director, Stephen W. Maly, Wojciech Strojwas, Andrzej J. |
| author_facet | Director, Stephen W. Maly, Wojciech Strojwas, Andrzej J. |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:59Z |
| institution | BVB |
| isbn | 9781461315216 |
| language | English |
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| physical | 1 Online-Ressource (XII, 292 p) |
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| publishDate | 1990 |
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| series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Director, Stephen W. Verfasser aut VLSI Design for Manufacturing: Yield Enhancement by Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas Boston, MA Springer US 1990 1 Online-Ressource (XII, 292 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 86 One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s 1\p DE-604 Entwurf (DE-588)4121208-3 s 2\p DE-604 Maly, Wojciech aut Strojwas, Andrzej J. aut Erscheint auch als Druck-Ausgabe 9781461288169 https://doi.org/10.1007/978-1-4613-1521-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Director, Stephen W. Maly, Wojciech Strojwas, Andrzej J. VLSI Design for Manufacturing: Yield Enhancement Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4117388-0 (DE-588)4179389-4 |
| title | VLSI Design for Manufacturing: Yield Enhancement |
| title_auth | VLSI Design for Manufacturing: Yield Enhancement |
| title_exact_search | VLSI Design for Manufacturing: Yield Enhancement |
| title_full | VLSI Design for Manufacturing: Yield Enhancement by Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas |
| title_fullStr | VLSI Design for Manufacturing: Yield Enhancement by Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas |
| title_full_unstemmed | VLSI Design for Manufacturing: Yield Enhancement by Stephen W. Director, Wojciech Maly, Andrzej J. Strojwas |
| title_short | VLSI Design for Manufacturing: Yield Enhancement |
| title_sort | vlsi design for manufacturing yield enhancement |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf VLSI Schaltungsentwurf |
| url | https://doi.org/10.1007/978-1-4613-1521-6 |
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