Reuse Methodology Manual: For System-on-a-Chip Designs
Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors a...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1999
|
| Ausgabe: | Second Edition |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs |
| Beschreibung: | 1 Online-Ressource (XXIII, 286 p) |
| ISBN: | 9781461550372 |
| DOI: | 10.1007/978-1-4615-5037-2 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045187182 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1999 |||| o||u| ||||||eng d | ||
| 020 | |a 9781461550372 |9 978-1-4615-5037-2 | ||
| 024 | 7 | |a 10.1007/978-1-4615-5037-2 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4615-5037-2 | ||
| 035 | |a (OCoLC)1184367053 | ||
| 035 | |a (DE-599)BVBBV045187182 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Keating, Michael |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Reuse Methodology Manual |b For System-on-a-Chip Designs |c by Michael Keating, Pierre Bricaud |
| 250 | |a Second Edition | ||
| 264 | 1 | |a Boston, MA |b Springer US |c 1999 | |
| 300 | |a 1 Online-Ressource (XXIII, 286 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 520 | |a Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Computer Hardware | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer hardware | |
| 650 | 4 | |a Computer-aided engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronic circuits | |
| 650 | 0 | 7 | |a System-on-Chip |0 (DE-588)4740357-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Softwarewiederverwendung |0 (DE-588)4225989-7 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a System-on-Chip |0 (DE-588)4740357-3 |D s |
| 689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | 1 | |a Softwarewiederverwendung |0 (DE-588)4225989-7 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Bricaud, Pierre |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461372899 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-5037-2 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030576360 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4615-5037-2 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178879032590336 |
|---|---|
| any_adam_object | |
| author | Keating, Michael Bricaud, Pierre |
| author_facet | Keating, Michael Bricaud, Pierre |
| author_role | aut aut |
| author_sort | Keating, Michael |
| author_variant | m k mk p b pb |
| building | Verbundindex |
| bvnumber | BV045187182 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4615-5037-2 (OCoLC)1184367053 (DE-599)BVBBV045187182 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-5037-2 |
| edition | Second Edition |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04127nmm a2200649zc 4500</leader><controlfield tag="001">BV045187182</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1999 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461550372</subfield><subfield code="9">978-1-4615-5037-2</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-5037-2</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-5037-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184367053</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045187182</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Keating, Michael</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Reuse Methodology Manual</subfield><subfield code="b">For System-on-a-Chip Designs</subfield><subfield code="c">by Michael Keating, Pierre Bricaud</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Second Edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1999</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XXIII, 286 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer Hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">System-on-Chip</subfield><subfield code="0">(DE-588)4740357-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Softwarewiederverwendung</subfield><subfield code="0">(DE-588)4225989-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">System-on-Chip</subfield><subfield code="0">(DE-588)4740357-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Softwarewiederverwendung</subfield><subfield code="0">(DE-588)4225989-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bricaud, Pierre</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461372899</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-5037-2</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030576360</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-5037-2</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045187182 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:59Z |
| institution | BVB |
| isbn | 9781461550372 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030576360 |
| oclc_num | 1184367053 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XXIII, 286 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Springer US |
| record_format | marc |
| spelling | Keating, Michael Verfasser aut Reuse Methodology Manual For System-on-a-Chip Designs by Michael Keating, Pierre Bricaud Second Edition Boston, MA Springer US 1999 1 Online-Ressource (XXIII, 286 p) txt rdacontent c rdamedia cr rdacarrier Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer Hardware Computer hardware Computer-aided engineering Electrical engineering Electronic circuits System-on-Chip (DE-588)4740357-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Softwarewiederverwendung (DE-588)4225989-7 gnd rswk-swf System-on-Chip (DE-588)4740357-3 s Entwurf (DE-588)4121208-3 s 1\p DE-604 VHDL (DE-588)4254792-1 s Softwarewiederverwendung (DE-588)4225989-7 s 2\p DE-604 Bricaud, Pierre aut Erscheint auch als Druck-Ausgabe 9781461372899 https://doi.org/10.1007/978-1-4615-5037-2 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Keating, Michael Bricaud, Pierre Reuse Methodology Manual For System-on-a-Chip Designs Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer Hardware Computer hardware Computer-aided engineering Electrical engineering Electronic circuits System-on-Chip (DE-588)4740357-3 gnd VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Softwarewiederverwendung (DE-588)4225989-7 gnd |
| subject_GND | (DE-588)4740357-3 (DE-588)4254792-1 (DE-588)4121208-3 (DE-588)4225989-7 |
| title | Reuse Methodology Manual For System-on-a-Chip Designs |
| title_auth | Reuse Methodology Manual For System-on-a-Chip Designs |
| title_exact_search | Reuse Methodology Manual For System-on-a-Chip Designs |
| title_full | Reuse Methodology Manual For System-on-a-Chip Designs by Michael Keating, Pierre Bricaud |
| title_fullStr | Reuse Methodology Manual For System-on-a-Chip Designs by Michael Keating, Pierre Bricaud |
| title_full_unstemmed | Reuse Methodology Manual For System-on-a-Chip Designs by Michael Keating, Pierre Bricaud |
| title_short | Reuse Methodology Manual |
| title_sort | reuse methodology manual for system on a chip designs |
| title_sub | For System-on-a-Chip Designs |
| topic | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer Hardware Computer hardware Computer-aided engineering Electrical engineering Electronic circuits System-on-Chip (DE-588)4740357-3 gnd VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Softwarewiederverwendung (DE-588)4225989-7 gnd |
| topic_facet | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer Hardware Computer hardware Computer-aided engineering Electrical engineering Electronic circuits System-on-Chip VHDL Entwurf Softwarewiederverwendung |
| url | https://doi.org/10.1007/978-1-4615-5037-2 |
| work_keys_str_mv | AT keatingmichael reusemethodologymanualforsystemonachipdesigns AT bricaudpierre reusemethodologymanualforsystemonachipdesigns |