Layout Minimization of CMOS Cells:
The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1992
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
160 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest |
| Beschreibung: | 1 Online-Ressource (XIII, 169 p) |
| ISBN: | 9781461536246 |
| DOI: | 10.1007/978-1-4615-3624-6 |
Internformat
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| author | Maziasz, Robert L. Hayes, John P. |
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| dewey-hundreds | 600 - Technology (Applied sciences) |
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| id | DE-604.BV045187172 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:59Z |
| institution | BVB |
| isbn | 9781461536246 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030576350 |
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| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XIII, 169 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1992 |
| publishDateSearch | 1992 |
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| record_format | marc |
| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Maziasz, Robert L. Verfasser aut Layout Minimization of CMOS Cells by Robert L. Maziasz, John P. Hayes Boston, MA Springer US 1992 1 Online-Ressource (XIII, 169 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 160 The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest Engineering Electrical Engineering Electrical engineering CMOS (DE-588)4010319-5 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Minimierung (DE-588)4251074-0 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf CMOS-Speicher (DE-588)4278777-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 s Minimierung (DE-588)4251074-0 s CMOS (DE-588)4010319-5 s 1\p DE-604 CMOS-Speicher (DE-588)4278777-4 s Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 3\p DE-604 Hayes, John P. aut Erscheint auch als Druck-Ausgabe 9781461366119 https://doi.org/10.1007/978-1-4615-3624-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Maziasz, Robert L. Hayes, John P. Layout Minimization of CMOS Cells Engineering Electrical Engineering Electrical engineering CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Minimierung (DE-588)4251074-0 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd CMOS-Speicher (DE-588)4278777-4 gnd |
| subject_GND | (DE-588)4010319-5 (DE-588)4179389-4 (DE-588)4251074-0 (DE-588)4264372-7 (DE-588)4278777-4 |
| title | Layout Minimization of CMOS Cells |
| title_auth | Layout Minimization of CMOS Cells |
| title_exact_search | Layout Minimization of CMOS Cells |
| title_full | Layout Minimization of CMOS Cells by Robert L. Maziasz, John P. Hayes |
| title_fullStr | Layout Minimization of CMOS Cells by Robert L. Maziasz, John P. Hayes |
| title_full_unstemmed | Layout Minimization of CMOS Cells by Robert L. Maziasz, John P. Hayes |
| title_short | Layout Minimization of CMOS Cells |
| title_sort | layout minimization of cmos cells |
| topic | Engineering Electrical Engineering Electrical engineering CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Minimierung (DE-588)4251074-0 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd CMOS-Speicher (DE-588)4278777-4 gnd |
| topic_facet | Engineering Electrical Engineering Electrical engineering CMOS Schaltungsentwurf Minimierung Layout Mikroelektronik CMOS-Speicher |
| url | https://doi.org/10.1007/978-1-4615-3624-6 |
| work_keys_str_mv | AT maziaszrobertl layoutminimizationofcmoscells AT hayesjohnp layoutminimizationofcmoscells |