Digit-Serial Computation:
Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can pr...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
316 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory |
| Beschreibung: | 1 Online-Ressource (XIII, 306 p) |
| ISBN: | 9781461523277 |
| DOI: | 10.1007/978-1-4615-2327-7 |
Internformat
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| 520 | |a Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory | ||
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Datensatz im Suchindex
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| author | Hartley, Richard Parhi, Keshab K. |
| author_facet | Hartley, Richard Parhi, Keshab K. |
| author_role | aut aut |
| author_sort | Hartley, Richard |
| author_variant | r h rh k k p kk kkp |
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| bvnumber | BV045187156 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4615-2327-7 (OCoLC)1053806788 (DE-599)BVBBV045187156 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-2327-7 |
| format | Electronic eBook |
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| id | DE-604.BV045187156 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:59Z |
| institution | BVB |
| isbn | 9781461523277 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030576334 |
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| physical | 1 Online-Ressource (XIII, 306 p) |
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| publishDate | 1995 |
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| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Hartley, Richard Verfasser aut Digit-Serial Computation by Richard Hartley, Keshab K. Parhi Boston, MA Springer US 1995 1 Online-Ressource (XIII, 306 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 316 Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Electrical engineering Electronic circuits Synchrones Schaltwerk (DE-588)4293676-7 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 s Synchrones Schaltwerk (DE-588)4293676-7 s 1\p DE-604 Parhi, Keshab K. aut Erscheint auch als Druck-Ausgabe 9781461359852 https://doi.org/10.1007/978-1-4615-2327-7 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Hartley, Richard Parhi, Keshab K. Digit-Serial Computation Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Electrical engineering Electronic circuits Synchrones Schaltwerk (DE-588)4293676-7 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| subject_GND | (DE-588)4293676-7 (DE-588)4113314-6 |
| title | Digit-Serial Computation |
| title_auth | Digit-Serial Computation |
| title_exact_search | Digit-Serial Computation |
| title_full | Digit-Serial Computation by Richard Hartley, Keshab K. Parhi |
| title_fullStr | Digit-Serial Computation by Richard Hartley, Keshab K. Parhi |
| title_full_unstemmed | Digit-Serial Computation by Richard Hartley, Keshab K. Parhi |
| title_short | Digit-Serial Computation |
| title_sort | digit serial computation |
| topic | Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Electrical engineering Electronic circuits Synchrones Schaltwerk (DE-588)4293676-7 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| topic_facet | Engineering Circuits and Systems Signal, Image and Speech Processing Electrical Engineering Electrical engineering Electronic circuits Synchrones Schaltwerk Digitale Signalverarbeitung |
| url | https://doi.org/10.1007/978-1-4615-2327-7 |
| work_keys_str_mv | AT hartleyrichard digitserialcomputation AT parhikeshabk digitserialcomputation |