Reasoning in Boolean Networks: Logic Synthesis and Verification using Testing Techniques
Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1997
|
| Schriftenreihe: | Frontiers in Electronic Testing
9 |
| Schlagworte: | |
| Online-Zugang: | BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques. While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems. Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material. Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies |
| Beschreibung: | 1 Online-Ressource (XVI, 230 p) |
| ISBN: | 9781475725728 |
| DOI: | 10.1007/978-1-4757-2572-8 |
Internformat
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| id | DE-604.BV045187106 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:58Z |
| institution | BVB |
| isbn | 9781475725728 |
| language | English |
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| physical | 1 Online-Ressource (XVI, 230 p) |
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| publishDate | 1997 |
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| publisher | Springer US |
| record_format | marc |
| series2 | Frontiers in Electronic Testing |
| spelling | Kunz, Wolfgang Verfasser aut Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques by Wolfgang Kunz, Dominik Stoffel Boston, MA Springer US 1997 1 Online-Ressource (XVI, 230 p) txt rdacontent c rdamedia cr rdacarrier Frontiers in Electronic Testing 9 Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques. While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems. Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material. Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Stoffel, Dominik aut Erscheint auch als Druck-Ausgabe 9781441951762 https://doi.org/10.1007/978-1-4757-2572-8 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Kunz, Wolfgang Stoffel, Dominik Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering |
| title | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques |
| title_auth | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques |
| title_exact_search | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques |
| title_full | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques by Wolfgang Kunz, Dominik Stoffel |
| title_fullStr | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques by Wolfgang Kunz, Dominik Stoffel |
| title_full_unstemmed | Reasoning in Boolean Networks Logic Synthesis and Verification using Testing Techniques by Wolfgang Kunz, Dominik Stoffel |
| title_short | Reasoning in Boolean Networks |
| title_sort | reasoning in boolean networks logic synthesis and verification using testing techniques |
| title_sub | Logic Synthesis and Verification using Testing Techniques |
| topic | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering |
| topic_facet | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering |
| url | https://doi.org/10.1007/978-1-4757-2572-8 |
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