Yield and Variability Optimization of Integrated Circuits:
Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual per...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters |
| Beschreibung: | 1 Online-Ressource (XVII, 234 p) |
| ISBN: | 9781461522256 |
| DOI: | 10.1007/978-1-4615-2225-6 |
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| 520 | |a Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters | ||
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Datensatz im Suchindex
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| author | Zhang, J. C. Styblinski, M. A. |
| author_facet | Zhang, J. C. Styblinski, M. A. |
| author_role | aut aut |
| author_sort | Zhang, J. C. |
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| bvnumber | BV045187082 |
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| ctrlnum | (ZDB-2-ENG)978-1-4615-2225-6 (OCoLC)1053845229 (DE-599)BVBBV045187082 |
| dewey-full | 621.3815 |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-2225-6 |
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It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. 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| spelling | Zhang, J. C. Verfasser aut Yield and Variability Optimization of Integrated Circuits by J. C. Zhang, M. A. Styblinski Boston, MA Springer US 1995 1 Online-Ressource (XVII, 234 p) txt rdacontent c rdamedia cr rdacarrier Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Ausbeute (DE-588)4208661-9 gnd rswk-swf 1\p (DE-588)4113937-9 Hochschulschrift gnd-content Integrierte Schaltung (DE-588)4027242-4 s Entwurf (DE-588)4121208-3 s Ausbeute (DE-588)4208661-9 s 2\p DE-604 Styblinski, M. A. aut Erscheint auch als Druck-Ausgabe 9781461359357 https://doi.org/10.1007/978-1-4615-2225-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Zhang, J. C. Styblinski, M. A. Yield and Variability Optimization of Integrated Circuits Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Ausbeute (DE-588)4208661-9 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4027242-4 (DE-588)4208661-9 (DE-588)4113937-9 |
| title | Yield and Variability Optimization of Integrated Circuits |
| title_auth | Yield and Variability Optimization of Integrated Circuits |
| title_exact_search | Yield and Variability Optimization of Integrated Circuits |
| title_full | Yield and Variability Optimization of Integrated Circuits by J. C. Zhang, M. A. Styblinski |
| title_fullStr | Yield and Variability Optimization of Integrated Circuits by J. C. Zhang, M. A. Styblinski |
| title_full_unstemmed | Yield and Variability Optimization of Integrated Circuits by J. C. Zhang, M. A. Styblinski |
| title_short | Yield and Variability Optimization of Integrated Circuits |
| title_sort | yield and variability optimization of integrated circuits |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Ausbeute (DE-588)4208661-9 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Entwurf Integrierte Schaltung Ausbeute Hochschulschrift |
| url | https://doi.org/10.1007/978-1-4615-2225-6 |
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