Integrated Circuit Defect-Sensitivity: Theory and Computational Models:
The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield esti...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1993
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, Microelectronics Manufacturing
208 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders |
| Beschreibung: | 1 Online-Ressource (XXIV, 167 p. 48 illus) |
| ISBN: | 9781461531586 |
| DOI: | 10.1007/978-1-4615-3158-6 |
Internformat
MARC
| LEADER | 00000nmm a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV045187011 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1993 |||| o||u| ||||||eng d | ||
| 020 | |a 9781461531586 |9 978-1-4615-3158-6 | ||
| 024 | 7 | |a 10.1007/978-1-4615-3158-6 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4615-3158-6 | ||
| 035 | |a (OCoLC)1053826844 | ||
| 035 | |a (DE-599)BVBBV045187011 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3 |2 23 | |
| 100 | 1 | |a Gyvez, José Pineda de |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Integrated Circuit Defect-Sensitivity: Theory and Computational Models |c by José Pineda de Gyvez |
| 264 | 1 | |a Boston, MA |b Springer US |c 1993 | |
| 300 | |a 1 Online-Ressource (XXIV, 167 p. 48 illus) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Springer International Series in Engineering and Computer Science, Microelectronics Manufacturing |v 208 | |
| 520 | |a The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 0 | 7 | |a Fehlererkennung |0 (DE-588)4133764-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | 1 | |a Fehlererkennung |0 (DE-588)4133764-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9780792393061 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-3158-6 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030576187 | ||
| 966 | e | |u https://doi.org/10.1007/978-1-4615-3158-6 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178878635180032 |
|---|---|
| any_adam_object | |
| author | Gyvez, José Pineda de |
| author_facet | Gyvez, José Pineda de |
| author_role | aut |
| author_sort | Gyvez, José Pineda de |
| author_variant | j p d g jpd jpdg |
| building | Verbundindex |
| bvnumber | BV045187011 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4615-3158-6 (OCoLC)1053826844 (DE-599)BVBBV045187011 |
| dewey-full | 621.3 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3 |
| dewey-search | 621.3 |
| dewey-sort | 3621.3 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-3158-6 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02819nmm a2200481zcb4500</leader><controlfield tag="001">BV045187011</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1993 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461531586</subfield><subfield code="9">978-1-4615-3158-6</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-3158-6</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-3158-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1053826844</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045187011</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Gyvez, José Pineda de</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Integrated Circuit Defect-Sensitivity: Theory and Computational Models</subfield><subfield code="c">by José Pineda de Gyvez</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1993</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XXIV, 167 p. 48 illus)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Springer International Series in Engineering and Computer Science, Microelectronics Manufacturing</subfield><subfield code="v">208</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Fehlererkennung</subfield><subfield code="0">(DE-588)4133764-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Fehlererkennung</subfield><subfield code="0">(DE-588)4133764-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9780792393061</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-3158-6</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030576187</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-3158-6</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045187011 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:58Z |
| institution | BVB |
| isbn | 9781461531586 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030576187 |
| oclc_num | 1053826844 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XXIV, 167 p. 48 illus) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1993 |
| publishDateSearch | 1993 |
| publishDateSort | 1993 |
| publisher | Springer US |
| record_format | marc |
| series2 | The Springer International Series in Engineering and Computer Science, Microelectronics Manufacturing |
| spelling | Gyvez, José Pineda de Verfasser aut Integrated Circuit Defect-Sensitivity: Theory and Computational Models by José Pineda de Gyvez Boston, MA Springer US 1993 1 Online-Ressource (XXIV, 167 p. 48 illus) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, Microelectronics Manufacturing 208 The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders Engineering Electrical Engineering Electrical engineering Fehlererkennung (DE-588)4133764-5 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Fehlererkennung (DE-588)4133764-5 s DE-604 Erscheint auch als Druck-Ausgabe 9780792393061 https://doi.org/10.1007/978-1-4615-3158-6 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Gyvez, José Pineda de Integrated Circuit Defect-Sensitivity: Theory and Computational Models Engineering Electrical Engineering Electrical engineering Fehlererkennung (DE-588)4133764-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4133764-5 (DE-588)4027242-4 |
| title | Integrated Circuit Defect-Sensitivity: Theory and Computational Models |
| title_auth | Integrated Circuit Defect-Sensitivity: Theory and Computational Models |
| title_exact_search | Integrated Circuit Defect-Sensitivity: Theory and Computational Models |
| title_full | Integrated Circuit Defect-Sensitivity: Theory and Computational Models by José Pineda de Gyvez |
| title_fullStr | Integrated Circuit Defect-Sensitivity: Theory and Computational Models by José Pineda de Gyvez |
| title_full_unstemmed | Integrated Circuit Defect-Sensitivity: Theory and Computational Models by José Pineda de Gyvez |
| title_short | Integrated Circuit Defect-Sensitivity: Theory and Computational Models |
| title_sort | integrated circuit defect sensitivity theory and computational models |
| topic | Engineering Electrical Engineering Electrical engineering Fehlererkennung (DE-588)4133764-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Engineering Electrical Engineering Electrical engineering Fehlererkennung Integrierte Schaltung |
| url | https://doi.org/10.1007/978-1-4615-3158-6 |
| work_keys_str_mv | AT gyvezjosepinedade integratedcircuitdefectsensitivitytheoryandcomputationalmodels |