Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recogni...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bhattacharya, Debashis (VerfasserIn), Hayes, John P. (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1990
Schriftenreihe:	The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 89
Schlagworte:	Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Simulation VLSI Test Prüftechnik Integrierte Schaltung
Online-Zugang:	BTU01 Volltext
Zusammenfassung:	Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models
Beschreibung:	1 Online-Ressource (XII, 160 p)
ISBN:	9781461315278
DOI:	10.1007/978-1-4613-1527-8