On Optimal Interconnections for VLSI:
On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algori...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1995
|
Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
301 |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design |
Beschreibung: | 1 Online-Ressource (XVIII, 286 p) |
ISBN: | 9781475723632 |
DOI: | 10.1007/978-1-4757-2363-2 |
Internformat
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490 | 0 | |a The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 301 | |
520 | |a On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design | ||
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Datensatz im Suchindex
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any_adam_object | |
author | Kahng, Andrew B. Robins, Gabriel |
author_facet | Kahng, Andrew B. Robins, Gabriel |
author_role | aut aut |
author_sort | Kahng, Andrew B. |
author_variant | a b k ab abk g r gr |
building | Verbundindex |
bvnumber | BV045186796 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4757-2363-2 (OCoLC)1053824687 (DE-599)BVBBV045186796 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4757-2363-2 |
format | Electronic eBook |
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id | DE-604.BV045186796 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:58Z |
institution | BVB |
isbn | 9781475723632 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575973 |
oclc_num | 1053824687 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XVIII, 286 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1995 |
publishDateSearch | 1995 |
publishDateSort | 1995 |
publisher | Springer US |
record_format | marc |
series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
spelling | Kahng, Andrew B. Verfasser aut On Optimal Interconnections for VLSI by Andrew B. Kahng, Gabriel Robins Boston, MA Springer US 1995 1 Online-Ressource (XVIII, 286 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 301 On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Routing (DE-588)4269073-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Routing (DE-588)4269073-0 s 1\p DE-604 Robins, Gabriel aut Erscheint auch als Druck-Ausgabe 9781441951458 https://doi.org/10.1007/978-1-4757-2363-2 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Kahng, Andrew B. Robins, Gabriel On Optimal Interconnections for VLSI Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Routing (DE-588)4269073-0 gnd VLSI (DE-588)4117388-0 gnd |
subject_GND | (DE-588)4269073-0 (DE-588)4117388-0 |
title | On Optimal Interconnections for VLSI |
title_auth | On Optimal Interconnections for VLSI |
title_exact_search | On Optimal Interconnections for VLSI |
title_full | On Optimal Interconnections for VLSI by Andrew B. Kahng, Gabriel Robins |
title_fullStr | On Optimal Interconnections for VLSI by Andrew B. Kahng, Gabriel Robins |
title_full_unstemmed | On Optimal Interconnections for VLSI by Andrew B. Kahng, Gabriel Robins |
title_short | On Optimal Interconnections for VLSI |
title_sort | on optimal interconnections for vlsi |
topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Routing (DE-588)4269073-0 gnd VLSI (DE-588)4117388-0 gnd |
topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Routing VLSI |
url | https://doi.org/10.1007/978-1-4757-2363-2 |
work_keys_str_mv | AT kahngandrewb onoptimalinterconnectionsforvlsi AT robinsgabriel onoptimalinterconnectionsforvlsi |