The Verilog Hardware Description Language:
Why learn and use Verilog if you're a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the tr...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1995
|
Ausgabe: | Second Edition |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Why learn and use Verilog if you're a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD's mandated language), PLl; TCP/IP versus OSI; the Intel X86 or PowerPC microprocessors versus DOD's many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD's Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate way Design Automation. It was Phil's third commercial logic simulator |
Beschreibung: | 1 Online-Ressource (XIX, 275 p) |
ISBN: | 9781475723656 |
DOI: | 10.1007/978-1-4757-2365-6 |
Internformat
MARC
LEADER | 00000nmm a2200000zc 4500 | ||
---|---|---|---|
001 | BV045186777 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180912s1995 |||| o||u| ||||||eng d | ||
020 | |a 9781475723656 |9 978-1-4757-2365-6 | ||
024 | 7 | |a 10.1007/978-1-4757-2365-6 |2 doi | |
035 | |a (ZDB-2-ENG)978-1-4757-2365-6 | ||
035 | |a (OCoLC)1184495322 | ||
035 | |a (DE-599)BVBBV045186777 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-634 | ||
082 | 0 | |a 621.3815 |2 23 | |
100 | 1 | |a Thomas, Donald E. |e Verfasser |4 aut | |
245 | 1 | 0 | |a The Verilog Hardware Description Language |c by Donald E. Thomas, Philip R. Moorby |
250 | |a Second Edition | ||
264 | 1 | |a Boston, MA |b Springer US |c 1995 | |
300 | |a 1 Online-Ressource (XIX, 275 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
520 | |a Why learn and use Verilog if you're a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD's mandated language), PLl; TCP/IP versus OSI; the Intel X86 or PowerPC microprocessors versus DOD's many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD's Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate way Design Automation. It was Phil's third commercial logic simulator | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Computer Hardware | |
650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Engineering | |
650 | 4 | |a Computer hardware | |
650 | 4 | |a Computer-aided engineering | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
700 | 1 | |a Moorby, Philip R. |4 aut | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781475723670 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4757-2365-6 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_Archiv | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030575954 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/978-1-4757-2365-6 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178878114037760 |
---|---|
any_adam_object | |
author | Thomas, Donald E. Moorby, Philip R. |
author_facet | Thomas, Donald E. Moorby, Philip R. |
author_role | aut aut |
author_sort | Thomas, Donald E. |
author_variant | d e t de det p r m pr prm |
building | Verbundindex |
bvnumber | BV045186777 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4757-2365-6 (OCoLC)1184495322 (DE-599)BVBBV045186777 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4757-2365-6 |
edition | Second Edition |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03321nmm a2200553zc 4500</leader><controlfield tag="001">BV045186777</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1995 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781475723656</subfield><subfield code="9">978-1-4757-2365-6</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4757-2365-6</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4757-2365-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184495322</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045186777</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Thomas, Donald E.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The Verilog Hardware Description Language</subfield><subfield code="c">by Donald E. Thomas, Philip R. Moorby</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Second Edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1995</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XIX, 275 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Why learn and use Verilog if you're a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD's mandated language), PLl; TCP/IP versus OSI; the Intel X86 or PowerPC microprocessors versus DOD's many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD's Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate way Design Automation. It was Phil's third commercial logic simulator</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer Hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Moorby, Philip R.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781475723670</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4757-2365-6</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030575954</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4757-2365-6</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV045186777 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:58Z |
institution | BVB |
isbn | 9781475723656 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575954 |
oclc_num | 1184495322 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XIX, 275 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1995 |
publishDateSearch | 1995 |
publishDateSort | 1995 |
publisher | Springer US |
record_format | marc |
spelling | Thomas, Donald E. Verfasser aut The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby Second Edition Boston, MA Springer US 1995 1 Online-Ressource (XIX, 275 p) txt rdacontent c rdamedia cr rdacarrier Why learn and use Verilog if you're a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD's mandated language), PLl; TCP/IP versus OSI; the Intel X86 or PowerPC microprocessors versus DOD's many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD's Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate way Design Automation. It was Phil's third commercial logic simulator Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s 1\p DE-604 Moorby, Philip R. aut Erscheint auch als Druck-Ausgabe 9781475723670 https://doi.org/10.1007/978-1-4757-2365-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Thomas, Donald E. Moorby, Philip R. The Verilog Hardware Description Language Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd |
subject_GND | (DE-588)4268385-3 |
title | The Verilog Hardware Description Language |
title_auth | The Verilog Hardware Description Language |
title_exact_search | The Verilog Hardware Description Language |
title_full | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
title_fullStr | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
title_full_unstemmed | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
title_short | The Verilog Hardware Description Language |
title_sort | the verilog hardware description language |
topic | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd |
topic_facet | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG |
url | https://doi.org/10.1007/978-1-4757-2365-6 |
work_keys_str_mv | AT thomasdonalde theveriloghardwaredescriptionlanguage AT moorbyphilipr theveriloghardwaredescriptionlanguage |