VHDL’92:
An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined e...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1993
|
Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
229 |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined environment is more complete, and the syntax is more regular and flexible. Discrepancies and known bugs of VHDL'87 have been fixed. However, the new VHDL'92 is compatible with VHDL'87, with some minor exceptions. This book presents the new VHDL'92 for the VHDL designer. New features ar explained and classified. Examples are provided, each new feature is given a rationale and its impact on design methodology, and performance is analysed. Where appropriate, pitfalls and traps are explained. The VHDL designer will quickly be able to find the feature needed to evaluate the benefits it brings, to modify previous VHDL'87 code to make it more efficient, more portable, and more flexible. VHDL'92 is the essential update for all VHDL designers and managers involved in electronic design |
Beschreibung: | 1 Online-Ressource (XVIII, 214 p) |
ISBN: | 9781461532460 |
DOI: | 10.1007/978-1-4615-3246-0 |
Internformat
MARC
LEADER | 00000nmm a2200000zcb4500 | ||
---|---|---|---|
001 | BV045186468 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180912s1993 |||| o||u| ||||||eng d | ||
020 | |a 9781461532460 |9 978-1-4615-3246-0 | ||
024 | 7 | |a 10.1007/978-1-4615-3246-0 |2 doi | |
035 | |a (ZDB-2-ENG)978-1-4615-3246-0 | ||
035 | |a (OCoLC)1184378993 | ||
035 | |a (DE-599)BVBBV045186468 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-634 | ||
082 | 0 | |a 621.3815 |2 23 | |
100 | 1 | |a Bergé, Jean-Michel |e Verfasser |4 aut | |
245 | 1 | 0 | |a VHDL’92 |c by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard |
264 | 1 | |a Boston, MA |b Springer US |c 1993 | |
300 | |a 1 Online-Ressource (XVIII, 214 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
490 | 0 | |a The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 229 | |
520 | |a An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined environment is more complete, and the syntax is more regular and flexible. Discrepancies and known bugs of VHDL'87 have been fixed. However, the new VHDL'92 is compatible with VHDL'87, with some minor exceptions. This book presents the new VHDL'92 for the VHDL designer. New features ar explained and classified. Examples are provided, each new feature is given a rationale and its impact on design methodology, and performance is analysed. Where appropriate, pitfalls and traps are explained. The VHDL designer will quickly be able to find the feature needed to evaluate the benefits it brings, to modify previous VHDL'87 code to make it more efficient, more portable, and more flexible. VHDL'92 is the essential update for all VHDL designers and managers involved in electronic design | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Systems Theory, Control | |
650 | 4 | |a Programming Languages, Compilers, Interpreters | |
650 | 4 | |a Engineering | |
650 | 4 | |a Programming languages (Electronic computers) | |
650 | 4 | |a Computer-aided engineering | |
650 | 4 | |a System theory | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
700 | 1 | |a Fonkoua, Alain |4 aut | |
700 | 1 | |a Maginot, Serge |4 aut | |
700 | 1 | |a Rouillard, Jacques |4 aut | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461364276 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-3246-0 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_Archiv | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030575645 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/978-1-4615-3246-0 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178877474406400 |
---|---|
any_adam_object | |
author | Bergé, Jean-Michel Fonkoua, Alain Maginot, Serge Rouillard, Jacques |
author_facet | Bergé, Jean-Michel Fonkoua, Alain Maginot, Serge Rouillard, Jacques |
author_role | aut aut aut aut |
author_sort | Bergé, Jean-Michel |
author_variant | j m b jmb a f af s m sm j r jr |
building | Verbundindex |
bvnumber | BV045186468 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4615-3246-0 (OCoLC)1184378993 (DE-599)BVBBV045186468 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4615-3246-0 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03316nmm a2200601zcb4500</leader><controlfield tag="001">BV045186468</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1993 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461532460</subfield><subfield code="9">978-1-4615-3246-0</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-3246-0</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-3246-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184378993</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045186468</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bergé, Jean-Michel</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">VHDL’92</subfield><subfield code="c">by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1993</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XVIII, 214 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="v">229</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined environment is more complete, and the syntax is more regular and flexible. Discrepancies and known bugs of VHDL'87 have been fixed. However, the new VHDL'92 is compatible with VHDL'87, with some minor exceptions. This book presents the new VHDL'92 for the VHDL designer. New features ar explained and classified. Examples are provided, each new feature is given a rationale and its impact on design methodology, and performance is analysed. Where appropriate, pitfalls and traps are explained. The VHDL designer will quickly be able to find the feature needed to evaluate the benefits it brings, to modify previous VHDL'87 code to make it more efficient, more portable, and more flexible. VHDL'92 is the essential update for all VHDL designers and managers involved in electronic design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems Theory, Control</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Programming Languages, Compilers, Interpreters</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Programming languages (Electronic computers)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">System theory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Fonkoua, Alain</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Maginot, Serge</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Rouillard, Jacques</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461364276</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-3246-0</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030575645</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-3246-0</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV045186468 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:57Z |
institution | BVB |
isbn | 9781461532460 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575645 |
oclc_num | 1184378993 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XVIII, 214 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1993 |
publishDateSearch | 1993 |
publishDateSort | 1993 |
publisher | Springer US |
record_format | marc |
series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
spelling | Bergé, Jean-Michel Verfasser aut VHDL’92 by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard Boston, MA Springer US 1993 1 Online-Ressource (XVIII, 214 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 229 An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete. The canonical simulator of VHDL is enriched by new mechanisms, the predefined environment is more complete, and the syntax is more regular and flexible. Discrepancies and known bugs of VHDL'87 have been fixed. However, the new VHDL'92 is compatible with VHDL'87, with some minor exceptions. This book presents the new VHDL'92 for the VHDL designer. New features ar explained and classified. Examples are provided, each new feature is given a rationale and its impact on design methodology, and performance is analysed. Where appropriate, pitfalls and traps are explained. The VHDL designer will quickly be able to find the feature needed to evaluate the benefits it brings, to modify previous VHDL'87 code to make it more efficient, more portable, and more flexible. VHDL'92 is the essential update for all VHDL designers and managers involved in electronic design Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Systems Theory, Control Programming Languages, Compilers, Interpreters Programming languages (Electronic computers) Computer-aided engineering System theory Electrical engineering Electronic circuits VHDL (DE-588)4254792-1 gnd rswk-swf VHDL (DE-588)4254792-1 s 1\p DE-604 Fonkoua, Alain aut Maginot, Serge aut Rouillard, Jacques aut Erscheint auch als Druck-Ausgabe 9781461364276 https://doi.org/10.1007/978-1-4615-3246-0 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Bergé, Jean-Michel Fonkoua, Alain Maginot, Serge Rouillard, Jacques VHDL’92 Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Systems Theory, Control Programming Languages, Compilers, Interpreters Programming languages (Electronic computers) Computer-aided engineering System theory Electrical engineering Electronic circuits VHDL (DE-588)4254792-1 gnd |
subject_GND | (DE-588)4254792-1 |
title | VHDL’92 |
title_auth | VHDL’92 |
title_exact_search | VHDL’92 |
title_full | VHDL’92 by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard |
title_fullStr | VHDL’92 by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard |
title_full_unstemmed | VHDL’92 by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard |
title_short | VHDL’92 |
title_sort | vhdl 92 |
topic | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Systems Theory, Control Programming Languages, Compilers, Interpreters Programming languages (Electronic computers) Computer-aided engineering System theory Electrical engineering Electronic circuits VHDL (DE-588)4254792-1 gnd |
topic_facet | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Systems Theory, Control Programming Languages, Compilers, Interpreters Programming languages (Electronic computers) Computer-aided engineering System theory Electrical engineering Electronic circuits VHDL |
url | https://doi.org/10.1007/978-1-4615-3246-0 |
work_keys_str_mv | AT bergejeanmichel vhdl92 AT fonkouaalain vhdl92 AT maginotserge vhdl92 AT rouillardjacques vhdl92 |