Wafer Scale Integration:
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with se...
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1989
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Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging |
Beschreibung: | 1 Online-Ressource (XX, 503 p) |
ISBN: | 9781461316213 |
DOI: | 10.1007/978-1-4613-1621-3 |
Internformat
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520 | |a Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
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650 | 4 | |a Microprocessors | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
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Datensatz im Suchindex
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dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
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dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4613-1621-3 |
format | Electronic eBook |
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id | DE-604.BV045186378 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:57Z |
institution | BVB |
isbn | 9781461316213 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575555 |
oclc_num | 1053826871 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XX, 503 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1989 |
publishDateSearch | 1989 |
publishDateSort | 1989 |
publisher | Springer US |
record_format | marc |
spelling | Wafer Scale Integration edited by Earl E. Swartzlander Boston, MA Springer US 1989 1 Online-Ressource (XX, 503 p) txt rdacontent c rdamedia cr rdacarrier Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging Engineering Circuits and Systems Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Wafer-Integration (DE-588)4226609-9 gnd rswk-swf Wafer-Integration (DE-588)4226609-9 s 1\p DE-604 Swartzlander, Earl E. edt Erscheint auch als Druck-Ausgabe 9781461288961 https://doi.org/10.1007/978-1-4613-1621-3 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Wafer Scale Integration Engineering Circuits and Systems Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Wafer-Integration (DE-588)4226609-9 gnd |
subject_GND | (DE-588)4226609-9 |
title | Wafer Scale Integration |
title_auth | Wafer Scale Integration |
title_exact_search | Wafer Scale Integration |
title_full | Wafer Scale Integration edited by Earl E. Swartzlander |
title_fullStr | Wafer Scale Integration edited by Earl E. Swartzlander |
title_full_unstemmed | Wafer Scale Integration edited by Earl E. Swartzlander |
title_short | Wafer Scale Integration |
title_sort | wafer scale integration |
topic | Engineering Circuits and Systems Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Wafer-Integration (DE-588)4226609-9 gnd |
topic_facet | Engineering Circuits and Systems Electrical Engineering Processor Architectures Microprocessors Electrical engineering Electronic circuits Wafer-Integration |
url | https://doi.org/10.1007/978-1-4613-1621-3 |
work_keys_str_mv | AT swartzlanderearle waferscaleintegration |