Logic Synthesis Using Synopsys:
Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compi...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 'classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided. Specifically, Logic Synthesis Using Synopsys will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog. Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools |
| Beschreibung: | 1 Online-Ressource (XXI, 304 p) |
| ISBN: | 9781475723700 |
| DOI: | 10.1007/978-1-4757-2370-0 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045186185 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1995 |||| o||u| ||||||eng d | ||
| 020 | |a 9781475723700 |9 978-1-4757-2370-0 | ||
| 024 | 7 | |a 10.1007/978-1-4757-2370-0 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4757-2370-0 | ||
| 035 | |a (OCoLC)1053828803 | ||
| 035 | |a (DE-599)BVBBV045186185 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Kurup, Pran |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logic Synthesis Using Synopsys |c by Pran Kurup, Taher Abbasi |
| 264 | 1 | |a Boston, MA |b Springer US |c 1995 | |
| 300 | |a 1 Online-Ressource (XXI, 304 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 520 | |a Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 'classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided. Specifically, Logic Synthesis Using Synopsys will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog. Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer-aided engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronic circuits | |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
| 689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Abbasi, Taher |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781475723724 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4757-2370-0 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030575362 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4757-2370-0 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178876886155264 |
|---|---|
| any_adam_object | |
| author | Kurup, Pran Abbasi, Taher |
| author_facet | Kurup, Pran Abbasi, Taher |
| author_role | aut aut |
| author_sort | Kurup, Pran |
| author_variant | p k pk t a ta |
| building | Verbundindex |
| bvnumber | BV045186185 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4757-2370-0 (OCoLC)1053828803 (DE-599)BVBBV045186185 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4757-2370-0 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03861nmm a2200613zc 4500</leader><controlfield tag="001">BV045186185</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1995 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781475723700</subfield><subfield code="9">978-1-4757-2370-0</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4757-2370-0</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4757-2370-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1053828803</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045186185</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kurup, Pran</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Logic Synthesis Using Synopsys</subfield><subfield code="c">by Pran Kurup, Taher Abbasi</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1995</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XXI, 304 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 'classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided. Specifically, Logic Synthesis Using Synopsys will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog. Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Abbasi, Taher</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781475723724</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4757-2370-0</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030575362</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4757-2370-0</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045186185 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:57Z |
| institution | BVB |
| isbn | 9781475723700 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575362 |
| oclc_num | 1053828803 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XXI, 304 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Springer US |
| record_format | marc |
| spelling | Kurup, Pran Verfasser aut Logic Synthesis Using Synopsys by Pran Kurup, Taher Abbasi Boston, MA Springer US 1995 1 Online-Ressource (XXI, 304 p) txt rdacontent c rdamedia cr rdacarrier Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 'classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided. Specifically, Logic Synthesis Using Synopsys will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog. Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 s Logischer Entwurf (DE-588)4168051-0 s 1\p DE-604 Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s 2\p DE-604 Abbasi, Taher aut Erscheint auch als Druck-Ausgabe 9781475723724 https://doi.org/10.1007/978-1-4757-2370-0 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Kurup, Pran Abbasi, Taher Logic Synthesis Using Synopsys Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logische Schaltung (DE-588)4131023-8 gnd Logischer Entwurf (DE-588)4168051-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4168051-0 (DE-588)4179389-4 (DE-588)4121208-3 |
| title | Logic Synthesis Using Synopsys |
| title_auth | Logic Synthesis Using Synopsys |
| title_exact_search | Logic Synthesis Using Synopsys |
| title_full | Logic Synthesis Using Synopsys by Pran Kurup, Taher Abbasi |
| title_fullStr | Logic Synthesis Using Synopsys by Pran Kurup, Taher Abbasi |
| title_full_unstemmed | Logic Synthesis Using Synopsys by Pran Kurup, Taher Abbasi |
| title_short | Logic Synthesis Using Synopsys |
| title_sort | logic synthesis using synopsys |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logische Schaltung (DE-588)4131023-8 gnd Logischer Entwurf (DE-588)4168051-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logische Schaltung Logischer Entwurf Schaltungsentwurf Entwurf |
| url | https://doi.org/10.1007/978-1-4757-2370-0 |
| work_keys_str_mv | AT kuruppran logicsynthesisusingsynopsys AT abbasitaher logicsynthesisusingsynopsys |