Defect and Fault Tolerance in VLSI Systems: Volume 2
Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield...
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Weitere Verfasser: | , , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1990
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Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21 |
Beschreibung: | 1 Online-Ressource (XIII, 316 p) |
ISBN: | 9781475799576 |
DOI: | 10.1007/978-1-4757-9957-6 |
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520 | |a Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21 | ||
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discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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isbn | 9781475799576 |
language | English |
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spelling | Defect and Fault Tolerance in VLSI Systems Volume 2 edited by C. H. Stapper, V. K. Jain, G. Saucier Boston, MA Springer US 1990 1 Online-Ressource (XIII, 316 p) txt rdacontent c rdamedia cr rdacarrier Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21 Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Stapper, C. H. edt Jain, V. K. edt Saucier, G. edt Erscheint auch als Druck-Ausgabe 9781475799590 https://doi.org/10.1007/978-1-4757-9957-6 Verlag URL des Erstveröffentlichers Volltext |
spellingShingle | Defect and Fault Tolerance in VLSI Systems Volume 2 Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
title | Defect and Fault Tolerance in VLSI Systems Volume 2 |
title_auth | Defect and Fault Tolerance in VLSI Systems Volume 2 |
title_exact_search | Defect and Fault Tolerance in VLSI Systems Volume 2 |
title_full | Defect and Fault Tolerance in VLSI Systems Volume 2 edited by C. H. Stapper, V. K. Jain, G. Saucier |
title_fullStr | Defect and Fault Tolerance in VLSI Systems Volume 2 edited by C. H. Stapper, V. K. Jain, G. Saucier |
title_full_unstemmed | Defect and Fault Tolerance in VLSI Systems Volume 2 edited by C. H. Stapper, V. K. Jain, G. Saucier |
title_short | Defect and Fault Tolerance in VLSI Systems |
title_sort | defect and fault tolerance in vlsi systems volume 2 |
title_sub | Volume 2 |
topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
url | https://doi.org/10.1007/978-1-4757-9957-6 |
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