Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic sto...
Gespeichert in:
| Weitere Verfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schlagworte: | |
| Online-Zugang: | BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized |
| Beschreibung: | 1 Online-Ressource (VIII, 400 p) |
| ISBN: | 9781475723533 |
| DOI: | 10.1007/978-1-4757-2353-3 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045185282 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1995 |||| o||u| ||||||eng d | ||
| 020 | |a 9781475723533 |9 978-1-4757-2353-3 | ||
| 024 | 7 | |a 10.1007/978-1-4757-2353-3 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4757-2353-3 | ||
| 035 | |a (OCoLC)1184500429 | ||
| 035 | |a (DE-599)BVBBV045185282 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3 |2 23 | |
| 245 | 1 | 0 | |a Analog Circuit Design |b Low-Power Low-Voltage, Integrated Filters and Smart Power |c edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing |
| 264 | 1 | |a Boston, MA |b Springer US |c 1995 | |
| 300 | |a 1 Online-Ressource (VIII, 400 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 520 | |a The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 0 | 7 | |a Filterschaltung |0 (DE-588)4113559-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Analogschaltung |0 (DE-588)4122796-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 655 | 7 | |8 1\p |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | |8 2\p |5 DE-604 | |
| 689 | 1 | 0 | |a Filterschaltung |0 (DE-588)4113559-3 |D s |
| 689 | 1 | |8 3\p |5 DE-604 | |
| 689 | 2 | 0 | |a Analogschaltung |0 (DE-588)4122796-7 |D s |
| 689 | 2 | |8 4\p |5 DE-604 | |
| 700 | 1 | |a Plassche, Rudy J. van de |4 edt | |
| 700 | 1 | |a Sansen, Willy M. C. |4 edt | |
| 700 | 1 | |a Huijsing, Johan H. |4 edt | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781441951496 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4757-2353-3 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030574460 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 4\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4757-2353-3 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178874986135552 |
|---|---|
| any_adam_object | |
| author2 | Plassche, Rudy J. van de Sansen, Willy M. C. Huijsing, Johan H. |
| author2_role | edt edt edt |
| author2_variant | r j v d p rjvd rjvdp w m c s wmc wmcs j h h jh jhh |
| author_facet | Plassche, Rudy J. van de Sansen, Willy M. C. Huijsing, Johan H. |
| building | Verbundindex |
| bvnumber | BV045185282 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4757-2353-3 (OCoLC)1184500429 (DE-599)BVBBV045185282 |
| dewey-full | 621.3 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3 |
| dewey-search | 621.3 |
| dewey-sort | 3621.3 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4757-2353-3 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03909nmm a2200601zc 4500</leader><controlfield tag="001">BV045185282</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1995 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781475723533</subfield><subfield code="9">978-1-4757-2353-3</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4757-2353-3</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4757-2353-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184500429</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045185282</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3</subfield><subfield code="2">23</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Analog Circuit Design</subfield><subfield code="b">Low-Power Low-Voltage, Integrated Filters and Smart Power</subfield><subfield code="c">edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1995</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (VIII, 400 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Filterschaltung</subfield><subfield code="0">(DE-588)4113559-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="8">1\p</subfield><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Filterschaltung</subfield><subfield code="0">(DE-588)4113559-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">4\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Plassche, Rudy J. van de</subfield><subfield code="4">edt</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sansen, Willy M. C.</subfield><subfield code="4">edt</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Huijsing, Johan H.</subfield><subfield code="4">edt</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781441951496</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4757-2353-3</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030574460</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">4\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4757-2353-3</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | 1\p (DE-588)1071861417 Konferenzschrift gnd-content |
| genre_facet | Konferenzschrift |
| id | DE-604.BV045185282 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:55Z |
| institution | BVB |
| isbn | 9781475723533 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030574460 |
| oclc_num | 1184500429 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (VIII, 400 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Springer US |
| record_format | marc |
| spelling | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing Boston, MA Springer US 1995 1 Online-Ressource (VIII, 400 p) txt rdacontent c rdamedia cr rdacarrier The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized Engineering Electrical Engineering Electrical engineering Filterschaltung (DE-588)4113559-3 gnd rswk-swf Analogschaltung (DE-588)4122796-7 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf 1\p (DE-588)1071861417 Konferenzschrift gnd-content Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 Filterschaltung (DE-588)4113559-3 s 3\p DE-604 Analogschaltung (DE-588)4122796-7 s 4\p DE-604 Plassche, Rudy J. van de edt Sansen, Willy M. C. edt Huijsing, Johan H. edt Erscheint auch als Druck-Ausgabe 9781441951496 https://doi.org/10.1007/978-1-4757-2353-3 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power Engineering Electrical Engineering Electrical engineering Filterschaltung (DE-588)4113559-3 gnd Analogschaltung (DE-588)4122796-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4113559-3 (DE-588)4122796-7 (DE-588)4179389-4 (DE-588)1071861417 |
| title | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power |
| title_auth | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power |
| title_exact_search | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power |
| title_full | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing |
| title_fullStr | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing |
| title_full_unstemmed | Analog Circuit Design Low-Power Low-Voltage, Integrated Filters and Smart Power edited by Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing |
| title_short | Analog Circuit Design |
| title_sort | analog circuit design low power low voltage integrated filters and smart power |
| title_sub | Low-Power Low-Voltage, Integrated Filters and Smart Power |
| topic | Engineering Electrical Engineering Electrical engineering Filterschaltung (DE-588)4113559-3 gnd Analogschaltung (DE-588)4122796-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Engineering Electrical Engineering Electrical engineering Filterschaltung Analogschaltung Schaltungsentwurf Konferenzschrift |
| url | https://doi.org/10.1007/978-1-4757-2353-3 |
| work_keys_str_mv | AT plasscherudyjvande analogcircuitdesignlowpowerlowvoltageintegratedfiltersandsmartpower AT sansenwillymc analogcircuitdesignlowpowerlowvoltageintegratedfiltersandsmartpower AT huijsingjohanh analogcircuitdesignlowpowerlowvoltageintegratedfiltersandsmartpower |