Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constitu...
Gespeichert in:
Weitere Verfasser: | , , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1996
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Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
367 |
Schlagworte: | |
Online-Zugang: | BTU01 URL des Erstveröffentlichers |
Zusammenfassung: | From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance. In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology |
Beschreibung: | 1 Online-Ressource (XVIII, 180 p) |
ISBN: | 9781461314110 |
DOI: | 10.1007/978-1-4613-1411-0 |
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520 | |a In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. | ||
520 | |a The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology | ||
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Datensatz im Suchindex
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author2 | Romdhane, Mohamed S. Ben Madisetti, Vijay K. Hines, John W. |
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discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4613-1411-0 |
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id | DE-604.BV045185249 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:55Z |
institution | BVB |
isbn | 9781461314110 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030574427 |
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owner_facet | DE-634 |
physical | 1 Online-Ressource (XVIII, 180 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1996 |
publishDateSearch | 1996 |
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publisher | Springer US |
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series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
spelling | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis edited by Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines Boston, MA Springer US 1996 1 Online-Ressource (XVIII, 180 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 367 From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance. In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Signal, Image and Speech Processing Computer-aided engineering Electrical engineering Electronic circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Entwurf (DE-588)4121208-3 s VHDL (DE-588)4254792-1 s 1\p DE-604 Romdhane, Mohamed S. Ben edt Madisetti, Vijay K. edt Hines, John W. edt Erscheint auch als Druck-Ausgabe 9781461286127 https://doi.org/10.1007/978-1-4613-1411-0 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Signal, Image and Speech Processing Computer-aided engineering Electrical engineering Electronic circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd Entwurf (DE-588)4121208-3 gnd VHDL (DE-588)4254792-1 gnd |
subject_GND | (DE-588)4122250-7 (DE-588)4121208-3 (DE-588)4254792-1 |
title | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis |
title_auth | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis |
title_exact_search | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis |
title_full | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis edited by Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines |
title_fullStr | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis edited by Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines |
title_full_unstemmed | Quick-Turnaround ASIC Design in VHDL Core-Based Behavioral Synthesis edited by Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines |
title_short | Quick-Turnaround ASIC Design in VHDL |
title_sort | quick turnaround asic design in vhdl core based behavioral synthesis |
title_sub | Core-Based Behavioral Synthesis |
topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Signal, Image and Speech Processing Computer-aided engineering Electrical engineering Electronic circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd Entwurf (DE-588)4121208-3 gnd VHDL (DE-588)4254792-1 gnd |
topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Signal, Image and Speech Processing Computer-aided engineering Electrical engineering Electronic circuits Kundenspezifische Schaltung Entwurf VHDL |
url | https://doi.org/10.1007/978-1-4613-1411-0 |
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