Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substan...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	McMillan, Kenneth L. (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Boston, MA Springer US 1993
Schlagworte:	Engineering Circuits and Systems Electrical Engineering Theory of Computation Computers Electrical engineering Electronic circuits Schaltungsentwurf Programmierbare logische Anordnung Schaltwerk Verifikation Personal Computer Korrektheit
Online-Zugang:	BTU01 Volltext
Zusammenfassung:	Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware. The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention
Beschreibung:	1 Online-Ressource (XVII, 194 p)
ISBN:	9781461531906
DOI:	10.1007/978-1-4615-3190-6