VLSI Placement and Global Routing Using Simulated Annealing:
From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1988
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
54 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in terchange algorithm |
| Beschreibung: | 1 Online-Ressource (XXVI, 278 p) |
| ISBN: | 9781461316978 |
| DOI: | 10.1007/978-1-4613-1697-8 |
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| spelling | Sechen, Carl Verfasser aut VLSI Placement and Global Routing Using Simulated Annealing by Carl Sechen Boston, MA Springer US 1988 1 Online-Ressource (XXVI, 278 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 54 From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in terchange algorithm Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Wärmebehandlung (DE-588)4064180-6 gnd rswk-swf Verdrahtung (DE-588)4187633-7 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Platzierung Mikroelektronik (DE-588)4197293-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Glühen (DE-588)4125136-2 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s VLSI (DE-588)4117388-0 s CAD (DE-588)4069794-0 s Verdrahtung (DE-588)4187633-7 s 1\p DE-604 Platzierung Mikroelektronik (DE-588)4197293-4 s 2\p DE-604 Simulation (DE-588)4055072-2 s 3\p DE-604 Wärmebehandlung (DE-588)4064180-6 s 4\p DE-604 Glühen (DE-588)4125136-2 s 5\p DE-604 Erscheint auch als Druck-Ausgabe 9781461289579 https://doi.org/10.1007/978-1-4613-1697-8 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Sechen, Carl VLSI Placement and Global Routing Using Simulated Annealing Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Wärmebehandlung (DE-588)4064180-6 gnd Verdrahtung (DE-588)4187633-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Platzierung Mikroelektronik (DE-588)4197293-4 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Glühen (DE-588)4125136-2 gnd Simulation (DE-588)4055072-2 gnd |
| subject_GND | (DE-588)4064180-6 (DE-588)4187633-7 (DE-588)4027242-4 (DE-588)4197293-4 (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)4125136-2 (DE-588)4055072-2 |
| title | VLSI Placement and Global Routing Using Simulated Annealing |
| title_auth | VLSI Placement and Global Routing Using Simulated Annealing |
| title_exact_search | VLSI Placement and Global Routing Using Simulated Annealing |
| title_full | VLSI Placement and Global Routing Using Simulated Annealing by Carl Sechen |
| title_fullStr | VLSI Placement and Global Routing Using Simulated Annealing by Carl Sechen |
| title_full_unstemmed | VLSI Placement and Global Routing Using Simulated Annealing by Carl Sechen |
| title_short | VLSI Placement and Global Routing Using Simulated Annealing |
| title_sort | vlsi placement and global routing using simulated annealing |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Wärmebehandlung (DE-588)4064180-6 gnd Verdrahtung (DE-588)4187633-7 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Platzierung Mikroelektronik (DE-588)4197293-4 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Glühen (DE-588)4125136-2 gnd Simulation (DE-588)4055072-2 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Wärmebehandlung Verdrahtung Integrierte Schaltung Platzierung Mikroelektronik VLSI CAD Glühen Simulation |
| url | https://doi.org/10.1007/978-1-4613-1697-8 |
| work_keys_str_mv | AT sechencarl vlsiplacementandglobalroutingusingsimulatedannealing |