The Verilog Hardware Description Language:
•• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Descripti...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1996
|
| Ausgabe: | Third Edition |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | •• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90 |
| Beschreibung: | 1 Online-Ressource (XIX, 310 p. 15 illus) |
| ISBN: | 9781475724646 |
| DOI: | 10.1007/978-1-4757-2464-6 |
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| 520 | |a •• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90 | ||
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Datensatz im Suchindex
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| isbn | 9781475724646 |
| language | English |
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| spelling | Thomas, Donald E. Verfasser aut The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby Third Edition Boston, MA Springer US 1996 1 Online-Ressource (XIX, 310 p. 15 illus) txt rdacontent c rdamedia cr rdacarrier •• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90 Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s 1\p DE-604 Moorby, Philip R. aut Erscheint auch als Druck-Ausgabe 9781475724660 https://doi.org/10.1007/978-1-4757-2464-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Thomas, Donald E. Moorby, Philip R. The Verilog Hardware Description Language Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | The Verilog Hardware Description Language |
| title_auth | The Verilog Hardware Description Language |
| title_exact_search | The Verilog Hardware Description Language |
| title_full | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
| title_fullStr | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
| title_full_unstemmed | The Verilog Hardware Description Language by Donald E. Thomas, Philip R. Moorby |
| title_short | The Verilog Hardware Description Language |
| title_sort | the verilog hardware description language |
| topic | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG |
| url | https://doi.org/10.1007/978-1-4757-2464-6 |
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