Parallel Algorithms and Architectures for DSP Applications:
Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major impro...
Gespeichert in:
Weitere Verfasser: | |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
1991
|
Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
149 |
Schlagworte: | |
Online-Zugang: | BTU01 Volltext |
Zusammenfassung: | Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance |
Beschreibung: | 1 Online-Ressource (XIII, 283 p) |
ISBN: | 9781461539964 |
DOI: | 10.1007/978-1-4615-3996-4 |
Internformat
MARC
LEADER | 00000nmm a2200000zcb4500 | ||
---|---|---|---|
001 | BV045184803 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180912s1991 |||| o||u| ||||||eng d | ||
020 | |a 9781461539964 |9 978-1-4615-3996-4 | ||
024 | 7 | |a 10.1007/978-1-4615-3996-4 |2 doi | |
035 | |a (ZDB-2-ENG)978-1-4615-3996-4 | ||
035 | |a (OCoLC)863700583 | ||
035 | |a (DE-599)BVBBV045184803 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-634 | ||
082 | 0 | |a 621.3815 |2 23 | |
245 | 1 | 0 | |a Parallel Algorithms and Architectures for DSP Applications |c edited by Magdy A. Bayoumi |
264 | 1 | |a Boston, MA |b Springer US |c 1991 | |
300 | |a 1 Online-Ressource (XIII, 283 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
490 | 0 | |a The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 149 | |
520 | |a Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Signal, Image and Speech Processing | |
650 | 4 | |a Processor Architectures | |
650 | 4 | |a Engineering | |
650 | 4 | |a Microprocessors | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
650 | 0 | 7 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Digitale Signalverarbeitung |0 (DE-588)4113314-6 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Paralleler Algorithmus |0 (DE-588)4193615-2 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
655 | 7 | |8 1\p |0 (DE-588)4143413-4 |a Aufsatzsammlung |2 gnd-content | |
689 | 0 | 0 | |a Digitale Signalverarbeitung |0 (DE-588)4113314-6 |D s |
689 | 0 | 1 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |D s |
689 | 0 | 2 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
689 | 0 | |8 2\p |5 DE-604 | |
689 | 1 | 0 | |a Digitale Signalverarbeitung |0 (DE-588)4113314-6 |D s |
689 | 1 | 1 | |a Paralleler Algorithmus |0 (DE-588)4193615-2 |D s |
689 | 1 | |8 3\p |5 DE-604 | |
700 | 1 | |a Bayoumi, Magdy A. |4 edt | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461367864 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-3996-4 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_Archiv | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030573980 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/978-1-4615-3996-4 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178873976356864 |
---|---|
any_adam_object | |
author2 | Bayoumi, Magdy A. |
author2_role | edt |
author2_variant | m a b ma mab |
author_facet | Bayoumi, Magdy A. |
building | Verbundindex |
bvnumber | BV045184803 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4615-3996-4 (OCoLC)863700583 (DE-599)BVBBV045184803 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4615-3996-4 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04233nmm a2200661zcb4500</leader><controlfield tag="001">BV045184803</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1991 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461539964</subfield><subfield code="9">978-1-4615-3996-4</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-3996-4</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-3996-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)863700583</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045184803</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Parallel Algorithms and Architectures for DSP Applications</subfield><subfield code="c">edited by Magdy A. Bayoumi</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XIII, 283 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="v">149</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Signal, Image and Speech Processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Processor Architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microprocessors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale Signalverarbeitung</subfield><subfield code="0">(DE-588)4113314-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Paralleler Algorithmus</subfield><subfield code="0">(DE-588)4193615-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="8">1\p</subfield><subfield code="0">(DE-588)4143413-4</subfield><subfield code="a">Aufsatzsammlung</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitale Signalverarbeitung</subfield><subfield code="0">(DE-588)4113314-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Digitale Signalverarbeitung</subfield><subfield code="0">(DE-588)4113314-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Paralleler Algorithmus</subfield><subfield code="0">(DE-588)4193615-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bayoumi, Magdy A.</subfield><subfield code="4">edt</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461367864</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-3996-4</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030573980</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-3996-4</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
genre | 1\p (DE-588)4143413-4 Aufsatzsammlung gnd-content |
genre_facet | Aufsatzsammlung |
id | DE-604.BV045184803 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:54Z |
institution | BVB |
isbn | 9781461539964 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030573980 |
oclc_num | 863700583 |
open_access_boolean | |
owner | DE-634 |
owner_facet | DE-634 |
physical | 1 Online-Ressource (XIII, 283 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 1991 |
publishDateSearch | 1991 |
publishDateSort | 1991 |
publisher | Springer US |
record_format | marc |
series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
spelling | Parallel Algorithms and Architectures for DSP Applications edited by Magdy A. Bayoumi Boston, MA Springer US 1991 1 Online-Ressource (XIII, 283 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 149 Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance Engineering Circuits and Systems Electrical Engineering Signal, Image and Speech Processing Processor Architectures Microprocessors Electrical engineering Electronic circuits Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf Paralleler Algorithmus (DE-588)4193615-2 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf 1\p (DE-588)4143413-4 Aufsatzsammlung gnd-content Digitale Signalverarbeitung (DE-588)4113314-6 s Parallelverarbeitung (DE-588)4075860-6 s Computerarchitektur (DE-588)4048717-9 s 2\p DE-604 Paralleler Algorithmus (DE-588)4193615-2 s 3\p DE-604 Bayoumi, Magdy A. edt Erscheint auch als Druck-Ausgabe 9781461367864 https://doi.org/10.1007/978-1-4615-3996-4 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Parallel Algorithms and Architectures for DSP Applications Engineering Circuits and Systems Electrical Engineering Signal, Image and Speech Processing Processor Architectures Microprocessors Electrical engineering Electronic circuits Parallelverarbeitung (DE-588)4075860-6 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd Computerarchitektur (DE-588)4048717-9 gnd |
subject_GND | (DE-588)4075860-6 (DE-588)4113314-6 (DE-588)4193615-2 (DE-588)4048717-9 (DE-588)4143413-4 |
title | Parallel Algorithms and Architectures for DSP Applications |
title_auth | Parallel Algorithms and Architectures for DSP Applications |
title_exact_search | Parallel Algorithms and Architectures for DSP Applications |
title_full | Parallel Algorithms and Architectures for DSP Applications edited by Magdy A. Bayoumi |
title_fullStr | Parallel Algorithms and Architectures for DSP Applications edited by Magdy A. Bayoumi |
title_full_unstemmed | Parallel Algorithms and Architectures for DSP Applications edited by Magdy A. Bayoumi |
title_short | Parallel Algorithms and Architectures for DSP Applications |
title_sort | parallel algorithms and architectures for dsp applications |
topic | Engineering Circuits and Systems Electrical Engineering Signal, Image and Speech Processing Processor Architectures Microprocessors Electrical engineering Electronic circuits Parallelverarbeitung (DE-588)4075860-6 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd Paralleler Algorithmus (DE-588)4193615-2 gnd Computerarchitektur (DE-588)4048717-9 gnd |
topic_facet | Engineering Circuits and Systems Electrical Engineering Signal, Image and Speech Processing Processor Architectures Microprocessors Electrical engineering Electronic circuits Parallelverarbeitung Digitale Signalverarbeitung Paralleler Algorithmus Computerarchitektur Aufsatzsammlung |
url | https://doi.org/10.1007/978-1-4615-3996-4 |
work_keys_str_mv | AT bayoumimagdya parallelalgorithmsandarchitecturesfordspapplications |