Systematic Design of Analog IP Blocks:
Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productiv...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
2003
|
Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing
738 |
Schlagworte: | |
Online-Zugang: | FHI01 BTU01 Volltext |
Zusammenfassung: | Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly |
Beschreibung: | 1 Online-Ressource (XII, 194 p) |
ISBN: | 9781475737073 |
DOI: | 10.1007/978-1-4757-3707-3 |
Internformat
MARC
LEADER | 00000nmm a2200000zcb4500 | ||
---|---|---|---|
001 | BV045149035 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180827s2003 |||| o||u| ||||||eng d | ||
020 | |a 9781475737073 |9 978-1-4757-3707-3 | ||
024 | 7 | |a 10.1007/978-1-4757-3707-3 |2 doi | |
035 | |a (ZDB-2-ENG)978-1-4757-3707-3 | ||
035 | |a (OCoLC)1050942847 | ||
035 | |a (DE-599)BVBBV045149035 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-573 |a DE-634 | ||
082 | 0 | |a 621.3815 |2 23 | |
100 | 1 | |a Vandenbussche, J. |e Verfasser |4 aut | |
245 | 1 | 0 | |a Systematic Design of Analog IP Blocks |c by J. Vandenbussche, G. Gielen, M. Steyaert |
264 | 1 | |a Boston, MA |b Springer US |c 2003 | |
300 | |a 1 Online-Ressource (XII, 194 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
490 | 0 | |a The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing |v 738 | |
520 | |a Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Engineering | |
650 | 4 | |a Computer-aided engineering | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronic circuits | |
700 | 1 | |a Gielen, G. |4 aut | |
700 | 1 | |a Steyaert, M. |4 aut | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781441953605 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4757-3707-3 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_2000/2004 | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030538734 | ||
966 | e | |u https://doi.org/10.1007/978-1-4757-3707-3 |l FHI01 |p ZDB-2-ENG |q ZDB-2-ENG_2000/2004 |x Verlag |3 Volltext | |
966 | e | |u https://doi.org/10.1007/978-1-4757-3707-3 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178820020830208 |
---|---|
any_adam_object | |
author | Vandenbussche, J. Gielen, G. Steyaert, M. |
author_facet | Vandenbussche, J. Gielen, G. Steyaert, M. |
author_role | aut aut aut |
author_sort | Vandenbussche, J. |
author_variant | j v jv g g gg m s ms |
building | Verbundindex |
bvnumber | BV045149035 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-1-4757-3707-3 (OCoLC)1050942847 (DE-599)BVBBV045149035 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4757-3707-3 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02843nmm a2200505zcb4500</leader><controlfield tag="001">BV045149035</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180827s2003 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781475737073</subfield><subfield code="9">978-1-4757-3707-3</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4757-3707-3</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4757-3707-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1050942847</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045149035</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Vandenbussche, J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Systematic Design of Analog IP Blocks</subfield><subfield code="c">by J. Vandenbussche, G. Gielen, M. Steyaert</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XII, 194 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing</subfield><subfield code="v">738</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gielen, G.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Steyaert, M.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781441953605</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4757-3707-3</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2000/2004</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030538734</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4757-3707-3</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_2000/2004</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4757-3707-3</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV045149035 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:02Z |
institution | BVB |
isbn | 9781475737073 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538734 |
oclc_num | 1050942847 |
open_access_boolean | |
owner | DE-573 DE-634 |
owner_facet | DE-573 DE-634 |
physical | 1 Online-Ressource (XII, 194 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 2003 |
publishDateSearch | 2003 |
publishDateSort | 2003 |
publisher | Springer US |
record_format | marc |
series2 | The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing |
spelling | Vandenbussche, J. Verfasser aut Systematic Design of Analog IP Blocks by J. Vandenbussche, G. Gielen, M. Steyaert Boston, MA Springer US 2003 1 Online-Ressource (XII, 194 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing 738 Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design. To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Gielen, G. aut Steyaert, M. aut Erscheint auch als Druck-Ausgabe 9781441953605 https://doi.org/10.1007/978-1-4757-3707-3 Verlag URL des Erstveröffentlichers Volltext |
spellingShingle | Vandenbussche, J. Gielen, G. Steyaert, M. Systematic Design of Analog IP Blocks Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits |
title | Systematic Design of Analog IP Blocks |
title_auth | Systematic Design of Analog IP Blocks |
title_exact_search | Systematic Design of Analog IP Blocks |
title_full | Systematic Design of Analog IP Blocks by J. Vandenbussche, G. Gielen, M. Steyaert |
title_fullStr | Systematic Design of Analog IP Blocks by J. Vandenbussche, G. Gielen, M. Steyaert |
title_full_unstemmed | Systematic Design of Analog IP Blocks by J. Vandenbussche, G. Gielen, M. Steyaert |
title_short | Systematic Design of Analog IP Blocks |
title_sort | systematic design of analog ip blocks |
topic | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits |
topic_facet | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits |
url | https://doi.org/10.1007/978-1-4757-3707-3 |
work_keys_str_mv | AT vandenbusschej systematicdesignofanalogipblocks AT gieleng systematicdesignofanalogipblocks AT steyaertm systematicdesignofanalogipblocks |