Synchronous Equivalence: Formal Methods for Embedded Systems
An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Traditionally, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechan...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2001
|
| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 Volltext |
| Zusammenfassung: | An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Traditionally, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechanical devices, or providing functionality that is not otherwise possible. The goal of this book is to investigate how formal methods can be applied to the domain of embedded system design. The emphasis is on the specification, representation, validation, and design exploration of such systems from a high-level perspective. The authors review the framework upon which the theories and experiments are based, and through which the formal methods are linked to synthesis and simulation. A formal verification methodology is formulated to verify general properties of the designs and demonstrate that this methodology is efficient in dealing with the problem of complexity and effective in finding bugs. However, manual intervention in the form of abstraction selection and separation of timing and functionality is required. It is conjectured that, for specific properties, efficient algorithms exist for completely automatic formal validations of systems. Synchronous Equivalence: Formal Methods for Embedded Systems presents a brand new formal approach to high-level equivalence analysis. It opens design exploration avenues previously uncharted. It is a work that can stand alone but at the same time is fully compatible with the synthesis and simulation framework described in another book by Kluwer Academic Publishers Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, by Balarin et al. Synchronous Equivalence: Formal Methods for Embedded Systems will be of interest to embedded system designers (automotive electronics, consumer electronics, and telecommunications), micro-controller designers, CAD developers and students, as well as IP providers, architecture platform designers, operating system providers, and designers of VLSI circuits and systems |
| Beschreibung: | 1 Online-Ressource (XI, 136 p) |
| ISBN: | 9781461516590 |
| DOI: | 10.1007/978-1-4615-1659-0 |
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| 520 | |a An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Traditionally, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechanical devices, or providing functionality that is not otherwise possible. The goal of this book is to investigate how formal methods can be applied to the domain of embedded system design. The emphasis is on the specification, representation, validation, and design exploration of such systems from a high-level perspective. The authors review the framework upon which the theories and experiments are based, and through which the formal methods are linked to synthesis and simulation. | ||
| 520 | |a A formal verification methodology is formulated to verify general properties of the designs and demonstrate that this methodology is efficient in dealing with the problem of complexity and effective in finding bugs. However, manual intervention in the form of abstraction selection and separation of timing and functionality is required. It is conjectured that, for specific properties, efficient algorithms exist for completely automatic formal validations of systems. Synchronous Equivalence: Formal Methods for Embedded Systems presents a brand new formal approach to high-level equivalence analysis. It opens design exploration avenues previously uncharted. It is a work that can stand alone but at the same time is fully compatible with the synthesis and simulation framework described in another book by Kluwer Academic Publishers Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, by Balarin et al. | ||
| 520 | |a Synchronous Equivalence: Formal Methods for Embedded Systems will be of interest to embedded system designers (automotive electronics, consumer electronics, and telecommunications), micro-controller designers, CAD developers and students, as well as IP providers, architecture platform designers, operating system providers, and designers of VLSI circuits and systems | ||
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| author | Hsieh, Harry Balarin, Felice Sangiovanni-Vincentelli, Alberto |
| author_facet | Hsieh, Harry Balarin, Felice Sangiovanni-Vincentelli, Alberto |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| isbn | 9781461516590 |
| language | English |
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| spelling | Hsieh, Harry Verfasser aut Synchronous Equivalence Formal Methods for Embedded Systems by Harry Hsieh, Felice Balarin, Alberto Sangiovanni-Vincentelli Boston, MA Springer US 2001 1 Online-Ressource (XI, 136 p) txt rdacontent c rdamedia cr rdacarrier An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Traditionally, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechanical devices, or providing functionality that is not otherwise possible. The goal of this book is to investigate how formal methods can be applied to the domain of embedded system design. The emphasis is on the specification, representation, validation, and design exploration of such systems from a high-level perspective. The authors review the framework upon which the theories and experiments are based, and through which the formal methods are linked to synthesis and simulation. A formal verification methodology is formulated to verify general properties of the designs and demonstrate that this methodology is efficient in dealing with the problem of complexity and effective in finding bugs. However, manual intervention in the form of abstraction selection and separation of timing and functionality is required. It is conjectured that, for specific properties, efficient algorithms exist for completely automatic formal validations of systems. Synchronous Equivalence: Formal Methods for Embedded Systems presents a brand new formal approach to high-level equivalence analysis. It opens design exploration avenues previously uncharted. It is a work that can stand alone but at the same time is fully compatible with the synthesis and simulation framework described in another book by Kluwer Academic Publishers Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, by Balarin et al. Synchronous Equivalence: Formal Methods for Embedded Systems will be of interest to embedded system designers (automotive electronics, consumer electronics, and telecommunications), micro-controller designers, CAD developers and students, as well as IP providers, architecture platform designers, operating system providers, and designers of VLSI circuits and systems Engineering Circuits and Systems Computing Methodologies Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Formale Methode (DE-588)4333722-3 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 s Formale Methode (DE-588)4333722-3 s 1\p DE-604 Balarin, Felice aut Sangiovanni-Vincentelli, Alberto aut Erscheint auch als Druck-Ausgabe 9781461356646 https://doi.org/10.1007/978-1-4615-1659-0 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Hsieh, Harry Balarin, Felice Sangiovanni-Vincentelli, Alberto Synchronous Equivalence Formal Methods for Embedded Systems Engineering Circuits and Systems Computing Methodologies Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Formale Methode (DE-588)4333722-3 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| subject_GND | (DE-588)4333722-3 (DE-588)4396978-1 |
| title | Synchronous Equivalence Formal Methods for Embedded Systems |
| title_auth | Synchronous Equivalence Formal Methods for Embedded Systems |
| title_exact_search | Synchronous Equivalence Formal Methods for Embedded Systems |
| title_full | Synchronous Equivalence Formal Methods for Embedded Systems by Harry Hsieh, Felice Balarin, Alberto Sangiovanni-Vincentelli |
| title_fullStr | Synchronous Equivalence Formal Methods for Embedded Systems by Harry Hsieh, Felice Balarin, Alberto Sangiovanni-Vincentelli |
| title_full_unstemmed | Synchronous Equivalence Formal Methods for Embedded Systems by Harry Hsieh, Felice Balarin, Alberto Sangiovanni-Vincentelli |
| title_short | Synchronous Equivalence |
| title_sort | synchronous equivalence formal methods for embedded systems |
| title_sub | Formal Methods for Embedded Systems |
| topic | Engineering Circuits and Systems Computing Methodologies Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Formale Methode (DE-588)4333722-3 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| topic_facet | Engineering Circuits and Systems Computing Methodologies Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Formale Methode Eingebettetes System |
| url | https://doi.org/10.1007/978-1-4615-1659-0 |
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