Logic Synthesis and Verification:
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this...
Gespeichert in:
| Weitere Verfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2002
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science
654 |
| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 Volltext |
| Zusammenfassung: | Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc |
| Beschreibung: | 1 Online-Ressource (XV, 454 p) |
| ISBN: | 9781461508175 |
| DOI: | 10.1007/978-1-4615-0817-5 |
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| 520 | |a Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc | ||
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| discipline | Informatik |
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| institution | BVB |
| isbn | 9781461508175 |
| language | English |
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| spelling | Logic Synthesis and Verification edited by Soha Hassoun, Tsutomu Sasao Boston, MA Springer US 2002 1 Online-Ressource (XV, 454 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science 654 Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc Computer Science Theory of Computation Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computers Computer-aided engineering Electrical engineering Electronic circuits Logiksynthese (DE-588)4348178-4 gnd rswk-swf Logiksynthese (DE-588)4348178-4 s 1\p DE-604 Hassoun, Soha edt Sasao, Tsutomu edt Erscheint auch als Druck-Ausgabe 9781461352532 https://doi.org/10.1007/978-1-4615-0817-5 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Logic Synthesis and Verification Computer Science Theory of Computation Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computers Computer-aided engineering Electrical engineering Electronic circuits Logiksynthese (DE-588)4348178-4 gnd |
| subject_GND | (DE-588)4348178-4 |
| title | Logic Synthesis and Verification |
| title_auth | Logic Synthesis and Verification |
| title_exact_search | Logic Synthesis and Verification |
| title_full | Logic Synthesis and Verification edited by Soha Hassoun, Tsutomu Sasao |
| title_fullStr | Logic Synthesis and Verification edited by Soha Hassoun, Tsutomu Sasao |
| title_full_unstemmed | Logic Synthesis and Verification edited by Soha Hassoun, Tsutomu Sasao |
| title_short | Logic Synthesis and Verification |
| title_sort | logic synthesis and verification |
| topic | Computer Science Theory of Computation Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computers Computer-aided engineering Electrical engineering Electronic circuits Logiksynthese (DE-588)4348178-4 gnd |
| topic_facet | Computer Science Theory of Computation Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computers Computer-aided engineering Electrical engineering Electronic circuits Logiksynthese |
| url | https://doi.org/10.1007/978-1-4615-0817-5 |
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