Verification Plans: The Five-Day Verification Strategy for Modern Hardware Verification Languages
Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplish...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2004
|
| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 Volltext |
| Zusammenfassung: | Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail |
| Beschreibung: | 1 Online-Ressource (XXII, 229 p) |
| ISBN: | 9781461504733 |
| DOI: | 10.1007/978-1-4615-0473-3 |
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| 520 | |a Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail | ||
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-0473-3 |
| format | Electronic eBook |
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| id | DE-604.BV045148848 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:02Z |
| institution | BVB |
| isbn | 9781461504733 |
| language | English |
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| spelling | James, Peet Verfasser aut Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages by Peet James Boston, MA Springer US 2004 1 Online-Ressource (XXII, 229 p) txt rdacontent c rdamedia cr rdacarrier Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail Engineering Circuits and Systems Computer Hardware Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits Erscheint auch als Druck-Ausgabe 9781461350941 https://doi.org/10.1007/978-1-4615-0473-3 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | James, Peet Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages Engineering Circuits and Systems Computer Hardware Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits |
| title | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages |
| title_auth | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages |
| title_exact_search | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages |
| title_full | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages by Peet James |
| title_fullStr | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages by Peet James |
| title_full_unstemmed | Verification Plans The Five-Day Verification Strategy for Modern Hardware Verification Languages by Peet James |
| title_short | Verification Plans |
| title_sort | verification plans the five day verification strategy for modern hardware verification languages |
| title_sub | The Five-Day Verification Strategy for Modern Hardware Verification Languages |
| topic | Engineering Circuits and Systems Computer Hardware Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Computer Hardware Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/978-1-4615-0473-3 |
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