Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction
1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devic...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2004
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing
841 |
| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 Volltext |
| Zusammenfassung: | 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance |
| Beschreibung: | 1 Online-Ressource (XIV, 154 p. 128 illus) |
| ISBN: | 9781402028496 |
| DOI: | 10.1007/978-1-4020-2849-6 |
Internformat
MARC
| LEADER | 00000nmm a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV045148640 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180827s2004 |||| o||u| ||||||eng d | ||
| 020 | |a 9781402028496 |9 978-1-4020-2849-6 | ||
| 024 | 7 | |a 10.1007/978-1-4020-2849-6 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4020-2849-6 | ||
| 035 | |a (OCoLC)1184501873 | ||
| 035 | |a (DE-599)BVBBV045148640 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-573 |a DE-634 | ||
| 082 | 0 | |a 621.3 |2 23 | |
| 100 | 1 | |a Meer, P. R. van der |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Low-Power Deep Sub-Micron CMOS Logic |b Sub-threshold Current Reduction |c by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund |
| 264 | 1 | |a Boston, MA |b Springer US |c 2004 | |
| 300 | |a 1 Online-Ressource (XIV, 154 p. 128 illus) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing |v 841 | |
| 520 | |a 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Engineering Design | |
| 650 | 4 | |a Theory of Computation | |
| 650 | 4 | |a Electronics and Microelectronics, Instrumentation | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computers | |
| 650 | 4 | |a Engineering design | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronics | |
| 650 | 4 | |a Microelectronics | |
| 650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
| 655 | 7 | |8 1\p |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |D s |
| 689 | 0 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Staveren, A. van |4 aut | |
| 700 | 1 | |a Roermund, A. H. M. van |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781475710571 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4020-2849-6 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_2000/2004 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030538339 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4020-2849-6 |l FHI01 |p ZDB-2-ENG |q ZDB-2-ENG_2000/2004 |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4020-2849-6 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178818968059904 |
|---|---|
| any_adam_object | |
| author | Meer, P. R. van der Staveren, A. van Roermund, A. H. M. van |
| author_facet | Meer, P. R. van der Staveren, A. van Roermund, A. H. M. van |
| author_role | aut aut aut |
| author_sort | Meer, P. R. van der |
| author_variant | p r v d m prvd prvdm a v s av avs a h m v r ahmv ahmvr |
| building | Verbundindex |
| bvnumber | BV045148640 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4020-2849-6 (OCoLC)1184501873 (DE-599)BVBBV045148640 |
| dewey-full | 621.3 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3 |
| dewey-search | 621.3 |
| dewey-sort | 3621.3 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4020-2849-6 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03898nmm a2200613zcb4500</leader><controlfield tag="001">BV045148640</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180827s2004 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402028496</subfield><subfield code="9">978-1-4020-2849-6</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4020-2849-6</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4020-2849-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184501873</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045148640</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Meer, P. R. van der</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Low-Power Deep Sub-Micron CMOS Logic</subfield><subfield code="b">Sub-threshold Current Reduction</subfield><subfield code="c">by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2004</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XIV, 154 p. 128 illus)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing</subfield><subfield code="v">841</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Theory of Computation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics and Microelectronics, Instrumentation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computers</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microelectronics</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="8">1\p</subfield><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Staveren, A. van</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Roermund, A. H. M. van</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781475710571</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4020-2849-6</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2000/2004</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030538339</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-2849-6</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_2000/2004</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-2849-6</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | 1\p (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV045148640 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:01Z |
| institution | BVB |
| isbn | 9781402028496 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538339 |
| oclc_num | 1184501873 |
| open_access_boolean | |
| owner | DE-573 DE-634 |
| owner_facet | DE-573 DE-634 |
| physical | 1 Online-Ressource (XIV, 154 p. 128 illus) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Springer US |
| record_format | marc |
| series2 | The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing |
| spelling | Meer, P. R. van der Verfasser aut Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund Boston, MA Springer US 2004 1 Online-Ressource (XIV, 154 p. 128 illus) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing 841 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance Engineering Electrical Engineering Engineering Design Theory of Computation Electronics and Microelectronics, Instrumentation Computers Engineering design Electrical engineering Electronics Microelectronics CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf 1\p (DE-588)4113937-9 Hochschulschrift gnd-content CMOS-Schaltung (DE-588)4148111-2 s 2\p DE-604 Staveren, A. van aut Roermund, A. H. M. van aut Erscheint auch als Druck-Ausgabe 9781475710571 https://doi.org/10.1007/978-1-4020-2849-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Meer, P. R. van der Staveren, A. van Roermund, A. H. M. van Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction Engineering Electrical Engineering Engineering Design Theory of Computation Electronics and Microelectronics, Instrumentation Computers Engineering design Electrical engineering Electronics Microelectronics CMOS-Schaltung (DE-588)4148111-2 gnd |
| subject_GND | (DE-588)4148111-2 (DE-588)4113937-9 |
| title | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction |
| title_auth | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction |
| title_exact_search | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction |
| title_full | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund |
| title_fullStr | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund |
| title_full_unstemmed | Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund |
| title_short | Low-Power Deep Sub-Micron CMOS Logic |
| title_sort | low power deep sub micron cmos logic sub threshold current reduction |
| title_sub | Sub-threshold Current Reduction |
| topic | Engineering Electrical Engineering Engineering Design Theory of Computation Electronics and Microelectronics, Instrumentation Computers Engineering design Electrical engineering Electronics Microelectronics CMOS-Schaltung (DE-588)4148111-2 gnd |
| topic_facet | Engineering Electrical Engineering Engineering Design Theory of Computation Electronics and Microelectronics, Instrumentation Computers Engineering design Electrical engineering Electronics Microelectronics CMOS-Schaltung Hochschulschrift |
| url | https://doi.org/10.1007/978-1-4020-2849-6 |
| work_keys_str_mv | AT meerprvander lowpowerdeepsubmicroncmoslogicsubthresholdcurrentreduction AT staverenavan lowpowerdeepsubmicroncmoslogicsubthresholdcurrentreduction AT roermundahmvan lowpowerdeepsubmicroncmoslogicsubthresholdcurrentreduction |