APA (7th ed.) Citation

Radecka, K., & Zilic, Z. (2003). Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Springer US. https://doi.org/10.1007/b105974

Chicago Style (17th ed.) Citation

Radecka, Katarzyna, and Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston, MA: Springer US, 2003. https://doi.org/10.1007/b105974.

MLA (9th ed.) Citation

Radecka, Katarzyna, and Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Springer US, 2003. https://doi.org/10.1007/b105974.