Verification by Error Modeling: Using Testing Techniques in Hardware Verification
1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, incl...
Gespeichert in:
Hauptverfasser: | , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
2003
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Schriftenreihe: | Frontiers in Electronic Testing
25 |
Schlagworte: | |
Online-Zugang: | FHI01 BTU01 Volltext |
Zusammenfassung: | 1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design |
Beschreibung: | 1 Online-Ressource (XV, 216 p) |
ISBN: | 9780306487392 |
DOI: | 10.1007/b105974 |
Internformat
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520 | |a 1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design | ||
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author | Radecka, Katarzyna Zilic, Zeljko |
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indexdate | 2024-07-10T08:10:01Z |
institution | BVB |
isbn | 9780306487392 |
language | English |
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spelling | Radecka, Katarzyna Verfasser aut Verification by Error Modeling Using Testing Techniques in Hardware Verification by Katarzyna Radecka, Zeljko Zilic Boston, MA Springer US 2003 1 Online-Ressource (XV, 216 p) txt rdacontent c rdamedia cr rdacarrier Frontiers in Electronic Testing 25 1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design Engineering Robotics and Automation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Computers Computer-aided engineering Robotics Automation Electrical engineering Electronic circuits Zilic, Zeljko aut Erscheint auch als Druck-Ausgabe 9781402076527 https://doi.org/10.1007/b105974 Verlag URL des Erstveröffentlichers Volltext |
spellingShingle | Radecka, Katarzyna Zilic, Zeljko Verification by Error Modeling Using Testing Techniques in Hardware Verification Engineering Robotics and Automation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Computers Computer-aided engineering Robotics Automation Electrical engineering Electronic circuits |
title | Verification by Error Modeling Using Testing Techniques in Hardware Verification |
title_auth | Verification by Error Modeling Using Testing Techniques in Hardware Verification |
title_exact_search | Verification by Error Modeling Using Testing Techniques in Hardware Verification |
title_full | Verification by Error Modeling Using Testing Techniques in Hardware Verification by Katarzyna Radecka, Zeljko Zilic |
title_fullStr | Verification by Error Modeling Using Testing Techniques in Hardware Verification by Katarzyna Radecka, Zeljko Zilic |
title_full_unstemmed | Verification by Error Modeling Using Testing Techniques in Hardware Verification by Katarzyna Radecka, Zeljko Zilic |
title_short | Verification by Error Modeling |
title_sort | verification by error modeling using testing techniques in hardware verification |
title_sub | Using Testing Techniques in Hardware Verification |
topic | Engineering Robotics and Automation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Computers Computer-aided engineering Robotics Automation Electrical engineering Electronic circuits |
topic_facet | Engineering Robotics and Automation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Computers Computer-aided engineering Robotics Automation Electrical engineering Electronic circuits |
url | https://doi.org/10.1007/b105974 |
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